A 10-Gb/s 0.18-μm CMOS Optical Receiver Front-End Amplifier

2013 ◽  
Vol 760-762 ◽  
pp. 115-119
Author(s):  
Wen Yuan Li ◽  
Rui Guo
Keyword(s):  
Low Voltage ◽  
Low Cost ◽  
Parasitic Capacitance ◽  
Optical Receiver ◽  
Cmos Process ◽  
Chip Area ◽  
Noise Interference ◽  
Limiting Amplifier ◽  
Front End ◽  
Voltage Swing

A fully integrated 10-Gb/s optical receiver analog front-end (AFE) design that includes a transimpedance amplifier (TIA) and a limiting amplifier (LA) is demonstrated to require less chip area and is suitable for both low-cost and low-voltage applications. The AFE is stimulation using a 0.18μm CMOS process. In order to avoid off-chip noise interference, the TIA and LA are dc-coupled on the chip instead of ac-coupled though a large external capacitor. The tiny photo current received by the receiver AFE is amplified to voltage swing of 400. The results indicate that, with a photodiode parasitic capacitance of 500fF and the bonding pad parasitic capacitance of 200fF between which a 2-mm bond wire is inserted at the input node, the AFE provides a conversion gain of up to 89.21 dB and 3 dB bandwidth of 9.78 GHz. Operating under a 1.8V supply, circuit power dissipation is 95 mW and its sensitivity is 18.5μA for BER of 10-12

A 10Gb/s Low-Power Front-End Amplifier for Optical Receiver in 0.18μm CMOS Technology

2012 ◽  
Vol 588-589 ◽  
pp. 872-875 ◽  
Author(s):  
Zhu Lei ◽  
Ying Mei Chen ◽  
Ling Tian ◽  
Li Zhang
Keyword(s):  
Cmos Technology ◽  
Optical Receiver ◽  
Transimpedance Amplifier ◽  
Chip Area ◽  
Limiting Amplifier ◽  
Front End ◽  
Active Feedback ◽  
Common Gate ◽  
The Common ◽  
Gain Stage

A Front-End Amplifier for the STM-64(10Gb/s) optical receiver in SDH system has been proposed in TSMC 0.18 μm CMOS technology. The common-gate feedforward configuration with an active inductor is employed in the input stage of transimpedance amplifier to increase the bandwidth. A 3-order interleaving active feedback configuration is employed to expand the bandwidth in the gain stage of transimpedance amplifier and limiting amplifier. Simulation results show that the output swing is 190mV (Vpp) when the input current varies from 20μA to 400μA. The power consumption is only 98.2mW with 1.8V power supply and the chip area is 496μm×480μm.

Design of a Digital Baseband Processor for UHF Tags

Electronics ◽  
2021 ◽  
Vol 10 (17) ◽  
pp. 2060
Author(s):  
Na Bai ◽  
Liang Wang ◽  
Yaohua Xu ◽  
Yi Wang
Keyword(s):  
Data Processing ◽  
Low Voltage ◽  
Random Number Generator ◽  
Digital Circuit ◽  
Cmos Process ◽  
Front End ◽  
Rf Front End ◽  
Machine Module ◽  
Baseband Processor ◽  
Digital Baseband

In this paper, we present a new digital baseband processor for UHF tags. It is a low-power and low-voltage digital circuit and adopts the Chinese military standard protocol GJB7377.1. The processor receives data or commands from the RF front-end and carries out various functions, such as receiving and writing data to memory, reading and sending memory data to the RF front-end and killing tags. The processor consists of thirteen main sub-modules: TPP decoding, clock management, random number generator, power management, memory controller, cyclic redundancy check, FM0 encoding, input data processing, output data processing, command detection module, initialization module, state machine module and controller. We use ModelSim for the TPP decoding simulation and communication simulation between tag and reader, and the simulation results meet the design requirements. The processor can be applied to UHF tags and has been taped out using a TSMC 0.18 um CMOS process.

Low-Power and Reference-Less Data and Clock Recovery Circuit for Visible Light Receivers

2018 ◽  
Author(s):  
Ming-Cheng Liu ◽  
Paul C.-P. Chao ◽  
Soh Sze Khiong
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Visible Light ◽  
Low Voltage ◽  
Supply Voltage ◽  
Clock And Data Recovery ◽  
Optical Receiver ◽  
Clock Recovery ◽  
Cmos Process ◽  
Rf Receiver

In this paper a low power all-digital clock and data recovery (ADCDR) with 1Mhz frequency has been proposed. The proposed circuit is designed for optical receiver circuit on the battery-less photovoltaic IoT (Internet of Things) tags. The conventional RF receiver has been replaced by the visible light optical receiver for battery-less IoT tags. With this proposed ADCDR a low voltage, low power consumption & tiny IoT tags can be fabricated. The proposed circuit achieve the maximum bandwidth of 1MHz, which is compatible with the commercial available LED and light sensor. The proposed circuit has been fabricated in TSMC 0.18um 1P6M standard CMOS process. Experimental results show that the power consumption of the optical receiver is approximately 5.58uW with a supply voltage of 1V and the data rate achieves 1Mbit/s. The lock time of the ADCDR is 0.893ms with 3.31ns RMS jitter period.

High Gain and Low Noise Single Balanced Wireless Receiver Front-End Circuit Design

2013 ◽  
Vol 284-287 ◽  
pp. 2647-2651
Author(s):  
Zhe Yang Huang ◽  
Che Cheng Huang ◽  
Jung Mao Lin ◽  
Chung Chih Hung
Keyword(s):  
Return Loss ◽  
Noise Figure ◽  
High Gain ◽  
Low Noise ◽  
Total Power ◽  
Cmos Process ◽  
Chip Area ◽  
Wireless Receiver ◽  
Front End ◽  
Total Power Consumption

This paper presents a wideband wireless receiver front-end for 3.1-5.0GHz band group-1 (BG-1) WiMedia application. The front-end circuits are designed in 0.18um standard CMOS process. The experimental results show the maximum conversion power gain is 45.5dB; minimum noise figure is 2.9dB. Input return loss is lower than -9.3dB and output return loss is lower than -6.8dB. The maximum LO conversion power is 0dBm. 3dB working frequency is 1.9GHz (3.1GHz-5.0GHz) Total power consumption is 24.3mW including LNA, mixer and all buffers. Total chip area is 1.27mm2 including dummy and pads.

A Digital-Based Ultra-Low-Voltage Pseudo-Differential CMOS Schmitt Trigger

2019 ◽  
Vol 29 (04) ◽  
pp. 2020002
Author(s):  
Yasin Bastan ◽  
Parviz Amiri
Keyword(s):  
Integrated Circuit ◽  
Low Voltage ◽  
Design Procedure ◽  
Schmitt Trigger ◽  
Input Voltage ◽  
Cmos Process ◽  
Differential Mode ◽  
Digital Cmos ◽  
Hysteresis Width ◽  
Chip Area

A digital-based Pseudo-differential Schmitt trigger is proposed in this paper which is suitable for ultra-low voltages and pure digital integrated circuit technologies. The proposed Schmitt trigger is implemented according to the design procedure of an analog Schmitt trigger and only using digital CMOS inverters. It is composed of a differential comparator consisting of two CMOS inverters and a cross-coupled inverter pair positive feedback which has simultaneously two outputs of noninverting and inverting. The proposed circuit is the only digital Schmitt trigger which operates in differential mode and its hysteresis center can be changed by the input voltage. Implementing the circuit in digital-based allows the proposed Schmitt trigger to operate in 0.4[Formula: see text]V ultra-low-voltage. Principle operation of the proposed circuit is discussed theoretically and using formulas and its performance is verified by simulation in TSMC 0.18[Formula: see text][Formula: see text]m CMOS process. The proposed circuit occupies only [Formula: see text][Formula: see text][Formula: see text]m2 chip area due to the very low number of transistors. The hysteresis width of the proposed Schmitt trigger is 205[Formula: see text]mV and consumes only 6.64[Formula: see text]nW power.

scholarly journals Energy Efficient Full Swing GDI based Adder Architecture for Arithmetic Applications

2021 ◽  
Author(s):  
Pratibha Aggarwal ◽  
Bharat Garg
Keyword(s):  
Low Power ◽  
Energy Efficient ◽  
Low Voltage ◽  
Critical Path ◽  
Full Adder ◽  
High Signal ◽  
Cmos Process ◽  
Process Technology ◽  
Wide Range ◽  
Voltage Swing

Abstract Adders are one of the most important digital components used in any arithmetic applications. Many improvements in past have been made to improve its architecture. In this paper, we present two new symmetric designs for Energy efficient full adder cells featuring GDI (Gate-Diffusion Input) logic. The main design objectives for these adder modules are to operate at Low-Power with reduced area but also provide full-voltage swing. In the first (AEG-FA) design, a new approach of Inverted and Non-Inverted Carry-ins were taken to give complementary Carry-out and Sum with desired performance. These were then applied in different combinations to form higher bit width Adder architecture. This provides a higher degree of design freedom to target a wide range of applications, hence reducing design efforts. The second (PEG-FA) design is based on conventional approach which tries to reduce the critical path delay and lower switching activity in GDI circuit, providing Low-Power and high speed digital component at full voltage swing circuit. Many of the previously reported adders in literature suffered from the problems of low-swing and high noise when operated at low supply voltages. These two new designs successfully operate at low voltage with high signal integrity and driving capability. In order to evaluate the performance of proposed full adders, we incorporated 8-bit ripple carry adders. The studied circuits are optimized for energy efficiency using 45 nm CMOS process technology. The comparison between these novel circuits with standard full adder cells shows improvement in terms of Area, Delay, Power and Power-Delay-Product (PDP), Area-Delay Product (ADP), Area-Power Product (APP). At architecture level proposed adder shows 12.8% over CMOS, 14.8% over hybrid and 11.4% over other GDI logic power savings, by having almost 55% reduction in area.

Output Voltage Sampling Circuit for Discontinuous Conduction Mode Flyback Pulse-Width Modulation Controller

2016 ◽  
Vol 25 (11) ◽  
pp. 1650140 ◽  
Author(s):  
Ling-Feng Shi ◽  
Zhen-Bo Shi ◽  
Sen Chen ◽  
Jian-Hui Xun
Keyword(s):  
Pulse Width ◽  
Output Voltage ◽  
Pulse Width Modulation ◽  
Low Voltage ◽  
Low Cost ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Discharge Time ◽  
Constant Output

Primary-side controlled pulse-width modulation (PWM) flyback converter has been widely used in low-power and low-voltage products for its simple structure and low cost. This paper presents a novel output voltage sampling circuit which considers the influence of the rectifier diode current on the output voltage sampling. The output voltage sampling circuit samples the output voltage at 85% of the secondary inductance discharge time [Formula: see text] of last cycle, which improves the accuracy of the output voltage sampling circuit. Besides, the circuit can also sample the secondary inductance discharge time [Formula: see text]. Finally, a chip has been fabricated in 0.6[Formula: see text][Formula: see text]m complementary metal-oxide semiconductor (CMOS) process, which is used in the presented output voltage sampling circuit in its internal circuit to simple output voltage and achieve constant output voltage.

scholarly journals A CMOS Optoelectronic Receiver IC with an On-Chip Avalanche Photodiode for Home-Monitoring LiDAR Sensors

Sensors ◽  
2021 ◽  
Vol 21 (13) ◽  
pp. 4364
Author(s):  
Ji-Eun Joo ◽  
Myung-Jae Lee ◽  
Sung Min Park
Keyword(s):  
Low Cost ◽  
Home Monitoring ◽  
Avalanche Photodiode ◽  
High Gain ◽  
Cmos Process ◽  
Detection Range ◽  
Noise Current ◽  
Limiting Amplifier ◽  
Circuit Techniques ◽  
On Chip

This paper presents an optoelectronic receiver (Rx) IC with an on-chip avalanche photodiode (APD) realized in a 0.18-mm CMOS process for the applications of home-monitoring light detection and ranging (LiDAR) sensors, where the on-chip CMOS P+/N-well APD was implemented to avoid the unwanted signal distortion from bondwires and electro-static discharge (ESD) protection diodes. Various circuit techniques are exploited in this work, such as the feedforward transimpedance amplifier for high gain, and a limiting amplifier with negative impedance compensation for wide bandwidth. Measured results demonstrate 93.4-dBW transimpedance gain, 790-MHz bandwidth, 12-pA/√Hz noise current spectral density, 6.74-mApp minimum detectable signal that corresponds to the maximum detection range of 10 m, and 56.5-mW power dissipation from a 1.8-V supply. This optoelectronic Rx IC provides a potential for a low-cost low-power solution in the applications of home-monitoring LiDAR sensors.

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