Fault-tolerant adaptive routing under permanent and temporary failures for many-core systems-on-chip

Current computing platforms encourage the integration of thousands of processing cores, and their interconnections, into a single chip. Mobile smartphones, IoT, embedded devices, desktops, and data centers use Many-Core Systems-on-Chip (SoCs) to exploit their compute power and parallelism to meet the dynamic workload requirements. Networks-on-Chip (NoCs) lead to scalable connectivity for diverse applications with distinct traffic patterns and data dependencies. However, when the system executes various applications in traditional NoCs—optimized and fixed at synthesis time—the interconnection nonconformity with the different applications’ requirements generates limitations in the performance. In the literature, NoC designs embraced the Software-Defined Networking (SDN) strategy to evolve into an adaptable interconnection solution for future chips. However, the works surveyed implement a partial Software-Defined Network-on-Chip (SDNoC) approach, leaving aside the SDN layered architecture that brings interoperability in conventional networking. This paper explores the SDNoC literature and classifies it regarding the desired SDN features that each work presents. Then, we described the challenges and opportunities detected from the literature survey. Moreover, we explain the motivation for an SDNoC approach, and we expose both SDN and SDNoC concepts and architectures. We observe that works in the literature employed an uncomplete layered SDNoC approach. This fact creates various fertile areas in the SDNoC architecture where researchers may contribute to Many-Core SoCs designs.

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Near-Optimal Thermal Monitoring Framework for Many-Core Systems-on-Chip

IEEE Transactions on Computers ◽

10.1109/tc.2015.2395423 ◽

2015 ◽

Vol 64 (11) ◽

pp. 3197-3209 ◽

Cited By ~ 2

Author(s):

Juri Ranieri ◽

Alessandro Vincenzi ◽

Amina Chebira ◽

David Atienza ◽

Martin Vetterli

Keyword(s):

Thermal Monitoring ◽

Systems On Chip ◽

Monitoring Framework ◽

On Chip ◽

Many Core

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How to Speed-Up Fault-Tolerant Clock Generation in VLSI Systems-on-Chip via Pipelining

2010 European Dependable Computing Conference ◽

10.1109/edcc.2010.35 ◽

2010 ◽

Cited By ~ 5

Author(s):

Matthias Függer ◽

Andreas Dielacher ◽

Ulrich Schmid

Keyword(s):

Fault Tolerant ◽

Clock Generation ◽

Systems On Chip ◽

Speed Up ◽

On Chip

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FoToNoC: A Folded Torus-Like Network-on-Chip Based Many-Core Systems-on-Chip in the Dark Silicon Era

IEEE Transactions on Parallel and Distributed Systems ◽

10.1109/tpds.2016.2643669 ◽

2017 ◽

Vol 28 (7) ◽

pp. 1905-1918 ◽

Cited By ~ 16

Author(s):

Lei Yang ◽

Weichen Liu ◽

Weiwen Jiang ◽

Mengquan Li ◽

Peng Chen ◽

...

Keyword(s):

Network On Chip ◽

Dark Silicon ◽

Systems On Chip ◽

On Chip ◽

Many Core

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A Network Adaptive Fault-Tolerant Routing Algorithm for Demanding Latency and Throughput Applications of Network-on-a-Chip Designs

Electronics ◽

10.3390/electronics9071076 ◽

2020 ◽

Vol 9 (7) ◽

pp. 1076 ◽

Cited By ~ 1

Author(s):

Zulqar Nain ◽

Rashid Ali ◽

Sheraz Anjum ◽

Muhammad Khalil Afzal ◽

Sung Won Kim

Keyword(s):

Fault Tolerant ◽

Current System ◽

Routing Algorithm ◽

Adaptive Routing ◽

Traffic Load ◽

Delivery Ratio ◽

Processing Elements ◽

System On A Chip ◽

On Chip ◽

Network On A Chip

Scalability is a significant issue in system-on-a-chip architectures because of the rapid increase in numerous on-chip resources. Moreover, hybrid processing elements demand diverse communication requirements, which system-on-a-chip architectures are unable to handle gracefully. Network-on-a-chip architectures have been proposed to address the scalability, contention, reusability, and congestion-related problems of current system-on-a-chip architectures. The reliability appears to be a challenging aspect of network-on-a-chip architectures because of the physical faults introduced in post-manufacturing processes. Therefore, to overcome such failures in network-on-a-chip architectures, fault-tolerant routing is critical. In this article, a network adaptive fault-tolerant routing algorithm is proposed, where the proposed algorithm enhances an efficient dynamic and adaptive routing algorithm. The proposed algorithm avoids livelocks because of its ability to select an alternate outport. It also manages to bypass congested regions of the network and balances the traffic load between outports that have an equal number of hop counts to its destination. Simulation results verified that in a fault-free scenario, the proposed solution outperformed a fault-tolerant XY by achieving a lower latency. At the same time, it attained a higher flit delivery ratio compared to the efficient dynamic and adaptive routing algorithm. Meanwhile, in the situation of a faulty network, the proposed algorithm could reach a higher flit delivery ratio of up to 18% while still consuming less power compared to the efficient dynamic and adaptive routing algorithm.

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CFPA: Congestion aware, fault tolerant and process variation aware adaptive routing algorithm for asynchronous Networks-on-Chip

Journal of Parallel and Distributed Computing ◽

10.1016/j.jpdc.2019.03.001 ◽

2019 ◽

Vol 128 ◽

pp. 151-166 ◽

Cited By ~ 3

Author(s):

Sayed T. Muhammad ◽

Mohamed Saad ◽

Ali A. El-Moursy ◽

Magdy A. El-Moursy ◽

Hesham F.A. Hamed

Keyword(s):

Fault Tolerant ◽

Process Variation ◽

Routing Algorithm ◽

Adaptive Routing ◽

Networks On Chip ◽

Asynchronous Networks ◽

On Chip ◽

Congestion Aware

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A Fault-Tolerant Deflection Routing for Network-on-Chip

Journal of Circuits System and Computers ◽

10.1142/s0218126617500372 ◽

2016 ◽

Vol 26 (03) ◽

pp. 1750037 ◽

Cited By ~ 3

Author(s):

Xiaofeng Zhou ◽

Lu Liu ◽

Zhangming Zhu

Keyword(s):

Fault Tolerant ◽

Network On Chip ◽

Deflection Routing ◽

Core System ◽

Routing Schemes ◽

Routing Performance ◽

Layout Area ◽

On Chip ◽

Many Core ◽

Redundant Fault

Network-on-Chip (NoC) has become a promising design methodology for the modern on-chip communication infrastructure of many-core system. To guarantee the reliability of traffic, effective fault-tolerant scheme is critical to NoC systems. In this paper, we propose a fault-tolerant deflection routing (FTDR) to address faults on links and router by redundancy technique. The proposed FTDR employs backup links and a redundant fault-tolerant unit (FTU) at router-level to sustain the traffic reliability of NoC. Experimental results show that the proposed FTDR yields an improvement of routing performance and fault-tolerant capability over the reported fault-tolerant routing schemes in average flit deflection rate, average packet latency, saturation throughput and reliability by up to 13.5%, 9.8%, 10.6% and 17.5%, respectively. The layout area and power consumption are increased merely 3.5% and 2.6%.

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