Resonant cavities using nanostructured front mirror for efficient LT-GaAs photoconductor operating at λ=1.55 μm

Author(s):  
M. Billet ◽  
P. Latzel ◽  
F. Pavanello ◽  
G. Ducournau ◽  
J. F. Lampin ◽  
...  
Keyword(s):  
APL Photonics ◽  
2016 ◽  
Vol 1 (7) ◽  
pp. 076102 ◽  
Author(s):  
M. Billet ◽  
P. Latzel ◽  
F. Pavanello ◽  
G. Ducournau ◽  
J.-F. Lampin ◽  
...  
Keyword(s):  

Author(s):  
Alain Claverie ◽  
Zuzanna Liliental-Weber

GaAs layers grown by MBE at low temperatures (in the 200°C range, LT-GaAs) have been reported to have very interesting electronic and transport properties. Previous studies have shown that, before annealing, the crystalline quality of the layers is related to the growth temperature. Lowering the temperature or increasing the layer thickness generally results in some columnar polycrystalline growth. For the best “temperature-thickness” combinations, the layers may be very As rich (up to 1.25%) resulting in an up to 0.15% increase of the lattice parameter, consistent with the excess As. Only after annealing are the technologically important semi-insulating properties of these layers observed. When annealed in As atmosphere at about 600°C a decrease of the lattice parameter to the substrate value is observed. TEM studies show formation of precipitates which are supposed to be As related since the average As concentration remains almost unchanged upon annealing.


2020 ◽  
Author(s):  
Yu Ji ◽  
Zongjun Shi ◽  
Ziqiang Yang ◽  
Feng Lan
Keyword(s):  

Author(s):  
Titus Oyedokun ◽  
Riana H. Geschke ◽  
Tinus Stander

Abstract We present a tunable planar groove gap waveguide (PGGWG) resonant cavity at Ka-band. The cavity demonstrates varactor loading and biasing without bridging wires or annular rings, as commonly is required in conventional substrate-integrated waveguide (SIW) resonant cavities. A detailed co-simulation strategy is also presented, with indicative parametric tuning data. Measured results indicate a 4.48% continuous frequency tuning range of 32.52–33.98 GHz and a Qu tuning range of 63–85, corresponding to the DC bias voltages of 0–16 V. Discrepancies between simulated and measured results are analyzed, and traced to process variation in the multi-layer printed circuit board stack, as well as unaccounted varactor parasitics and surface roughness.


2021 ◽  
Vol 103 (1) ◽  
Author(s):  
Ivan Cardea ◽  
Davide Grassani ◽  
Jeremy Upham ◽  
Sebastian A. Schulz ◽  
Kosmas L. Tsakmakidis ◽  
...  
Keyword(s):  

Author(s):  
Jessica Afalla ◽  
Elizabeth Ann Prieto ◽  
Karl Cedric Gonzales ◽  
Gerald Catindig ◽  
Valynn Katrine Mag-usara ◽  
...  

1991 ◽  
Vol 241 ◽  
Author(s):  
L.-W. Yin ◽  
J. Ibbetson ◽  
M. M. Hashemi ◽  
W. Jiang ◽  
S.-Y. Hu ◽  
...  

ABSTRACTDC characteristics of a GaAs MISFET structure using low-temperature GaAs (LTGaAs) as the gate insulator were investigated. MISFETs with different gate to channel separation (d) were fabricated. The dependence of four important device parameters such as gate-drain breakdown voltage (VBR), channel current at zero gate bias (Idss), transconductance (gm), and gate-drain turn-on voltage (Von) on the gate insulator thickness were analyzed. It was observed that (a) in terms of Idss and gin, the LT-GaAs gate insulator behaves like an undoped regular GaAs layer and (b) in terms of VBR and Von, the LT-GaAs gate insulator behaves as a trap dominated layer.


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