Novel high-frequency continuous-time low-pass OTA based filters

2002 ◽  
Author(s):  
B.M. Al-Hashimi ◽  
J.K. Fidler
2017 ◽  
Vol E100.C (10) ◽  
pp. 858-865 ◽  
Author(s):  
Yohei MORISHITA ◽  
Koichi MIZUNO ◽  
Junji SATO ◽  
Koji TAKINAMI ◽  
Kazuaki TAKAHASHI

1993 ◽  
Vol 47 (4) ◽  
pp. 489-500 ◽  
Author(s):  
J. F. Power ◽  
M. C. Prystay

Homodyne photothermal spectrometry (HPS) is a very wide bandwidth signal recovery technique which uses many of the elements of lock-in detection at very low cost. The method uses a frequency sweep, with a high-frequency bandwidth of up to 10 MHz, to excite a linear photothermal system. The response sweep of the photothermal system is downshifted into a bandwidth of a few kilohertz by means of in-phase mixing with the excitation sweep with the use of a four-quadrant double-balanced mixer and a low-pass filter. Under conditions derived from theory, the filter output gives a good approximation to the real part of the photothermal system's frequency response, dispersed as a function of time. From a recording of this signal, the frequency and impulse response of the photothermal system are rapidly recovered at very high resolution. The method has been tested with the use of laser photopyroelectric effect spectrometry and provides an inexpensive, convenient method for the recovery of high-frequency photothermal signals.


Author(s):  
Eka Fitrah Pribadi ◽  
Rajeev Kumar Pandey ◽  
Paul C.-P. Chao

Abstract A high-resolution, low offset delta-sigma analog to digital converter for detecting photoplethysmography (PPG) signal is presented in this study. The PPG signal is a bio-optical signal incorporated with heart functionality and located in the range of 0.1–10 Hz. The location to get PPG signal is on a pulsating artery. Thus the delta-sigma analog-to-digital (DS ADC) converter is designed specifically in that range. However, the DS ADC circuitry suffers from 1/f noise under 10 Hz frequency range. A chopper based operational amplifier is implemented in DS ADC to push the 1/f noise into high-frequency noise. The dc offset of the operational amplifier is also pushed to the high-frequency region. The DS ADC circuitry consists of a second-order continuous-time delta-sigma modulator. The delta-sigma modulator circuitry is designed and simulated using TSMC 180 nm technology. The continuous-time delta-sigma modulator active area layout is 746μm × 399 μm and fabricated using TSMC 180 nm technology. It operates in 100 Hz bandwidth and 4096 over-sampling ratios. The SFDR of the circuit is above 70 dB. The power consumption of the delta-sigma modulator is 35.61μW. The simulation is performed in three different kinds of corner, SS, TT, and FF corner, to guarantee the circuitry works in different conditions.


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