A fast-lock synchronous multi-phase clock generator based on a time-to-digital converter

2009 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2009.5117670 ◽

2009 ◽

Author(s):

Dongsuk Shin ◽

Jabeom Koo ◽

Won-Joo Yun ◽

Young Jung Choi ◽

Chulwoo Kim

Keyword(s):

Clock Generator ◽

Digital Converter ◽

Time To Digital Converter ◽

Phase Clock ◽

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An 8.8-GS/s 6-bit CMOS Time-Interleaved Flash Analog-to-Digital Converter with Multi-Phase Clock Generator

IEICE Transactions on Electronics ◽

10.1093/ietele/e90-c.6.1156 ◽

2007 ◽

Vol E90-C (6) ◽

pp. 1156-1164 ◽

Author(s):

Y.-C. JANG ◽

J.-H. BAE ◽

S.-H. PARK ◽

J.-Y. SIM ◽

H.-J. PARK

Keyword(s):

Clock Generator ◽

Analog To Digital Converter ◽

Digital Converter ◽

Analog To Digital ◽

Phase Clock ◽

Multi Phase ◽

Time Interleaved

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A high-resolution time-to-digital converter based on multi-phase clock implement in field-programmable-gate-array

2012 18th IEEE-NPSS Real Time Conference ◽

10.1109/rtc.2012.6418217 ◽

2012 ◽

Author(s):

Zhoujiancheng Yin ◽

Shubin Liu ◽

Xinjun Hao ◽

Shanshan Gao ◽

Qi An

Keyword(s):

High Resolution ◽

Field Programmable Gate Array ◽

Digital Converter ◽

Resolution Time ◽

Time To Digital Converter ◽

Field Programmable ◽

Phase Clock ◽

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A 256-channel multi-phase clock sampling-based time-to-digital converter implemented in a Kintex-7 FPGA

2016 IEEE International Instrumentation and Measurement Technology Conference Proceedings ◽

10.1109/i2mtc.2016.7520401 ◽

2016 ◽

Author(s):

Yonggang Wang ◽

Peng Kuang ◽

Chong Liu

Keyword(s):

Digital Converter ◽

Time To Digital Converter ◽

Phase Clock ◽

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A low-jitter skew-calibrated multi-phase clock generator for time-interleaved applications

2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177) ◽

10.1109/isscc.2001.912690 ◽

2002 ◽

Author(s):

Lin Wu ◽

W.C. Black

Keyword(s):

Clock Generator ◽

Phase Clock ◽

Multi Phase ◽

Time Interleaved

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A multi-phase clock generator for high accuracy fully differential switched capacitor readout circuit

2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC) ◽

10.1109/edssc.2017.8126559 ◽

2017 ◽

Author(s):

Xinquan Lai ◽

Kai Zhang ◽

Chen Liu ◽

Yuheng Wang ◽

Longjie Zhong ◽

...

Keyword(s):

High Accuracy ◽

Switched Capacitor ◽

Readout Circuit ◽

Clock Generator ◽

Fully Differential ◽

Phase Clock ◽

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A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop

13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems ◽

10.1109/ddecs.2010.5491766 ◽

2010 ◽

Author(s):

Kuo-Hsing Cheng ◽

Chang-Chien Hu ◽

Jen-Chieh Liu ◽

Hong-Yi Huang

Keyword(s):

Phase Locked Loop ◽

Digital Converter ◽

Time To Digital Converter ◽

Digital Phase ◽

Phase Sampling ◽

Time Amplifier ◽

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A multi-phase clock design for super high-speed time interleaved analog-to-digital converter

Anti-counterfeiting, Security, and Identification ◽

10.1109/icasid.2012.6325291 ◽

2012 ◽

Author(s):

Yu-Han Gao ◽

Yong-Lu Wang ◽

Zheng-Ping Zhang

Keyword(s):

Analog To Digital Converter ◽

Digital Converter ◽

Analog To Digital ◽

Phase Clock ◽

Multi Phase ◽

Time Interleaved

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A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET

2019 IEEE Custom Integrated Circuits Conference (CICC) ◽

10.1109/cicc.2019.8780177 ◽

2019 ◽

Author(s):

Sanquan Song ◽

John Poulton ◽

Xi Chen ◽

Brian Zimmer ◽

Stephen G. Tell ◽

...

Keyword(s):

Clock Generator ◽

Phase Clock ◽

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An asynchronous SAR ADC with gate-controlled ring oscillator for multi-phase clock generator

2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) ◽

10.1109/icsict.2014.7021295 ◽

2014 ◽

Author(s):

Jifang Wu ◽

Fule Li ◽

Chun Zhang

Keyword(s):

Sar Adc ◽

Ring Oscillator ◽

Clock Generator ◽

Phase Clock ◽

Asynchronous Sar ◽

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High-resolution and wide-dynamic range time-to-digital converter with a multi-phase cyclic Vernier delay line

2013 Proceedings of the ESSCIRC (ESSCIRC) ◽

10.1109/esscirc.2013.6649135 ◽

2013 ◽

Author(s):

Mino Kim ◽

Woo-Yeol Shin ◽

Gi-Moon Hong ◽

Jihwan Park ◽

Joo-Hyung Chae ◽

...

Keyword(s):

High Resolution ◽

Dynamic Range ◽

Digital Converter ◽

Wide Dynamic Range ◽

Time To Digital Converter ◽

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