Power, Performance, Area and Cost Analysis of Memory-on-Logic Face-to-Face Bonded 3D Processor Designs

Author(s):  
Anthony Agnesina ◽  
Moritz Brunion ◽  
Jinwoo Kim ◽  
Alberto Garcia-Ortiz ◽  
Dragomir Milojevic ◽  
...  
2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Goutham Arutchelvan ◽  
Quentin Smets ◽  
Devin Verreck ◽  
Zubair Ahmed ◽  
Abhinav Gaur ◽  
...  

AbstractTwo-dimensional semiconducting materials are considered as ideal candidates for ultimate device scaling. However, a systematic study on the performance and variability impact of scaling the different device dimensions is still lacking. Here we investigate the scaling behavior across 1300 devices fabricated on large-area grown MoS2 material with channel length down to 30 nm, contact length down to 13 nm and capacitive effective oxide thickness (CET) down to 1.9 nm. These devices show best-in-class performance with transconductance of 185 μS/μm and a minimum subthreshold swing (SS) of 86 mV/dec. We find that scaling the top-contact length has no impact on the contact resistance and electrostatics of three monolayers MoS2 transistors, because edge injection is dominant. Further, we identify that SS degradation occurs at short channel length and can be mitigated by reducing the CET and lowering the Schottky barrier height. Finally, using a power performance area (PPA) analysis, we present a roadmap of material improvements to make 2D devices competitive with silicon gate-all-around devices.


2021 ◽  
Author(s):  
Goutham Arutchelvan ◽  
Quentin Smets ◽  
Devin Verreck ◽  
Zubair Ahmed ◽  
Abhinav Gaur ◽  
...  

Abstract Two-dimensional semiconducting materials are considered as ideal candidates for ultimate device scaling. However, a systematic study on the performance and variability impact of scaling the different device dimensions is still lacking. Here we investigate the scaling behavior across 1300 devices fabricated on large-area grown MoS2 material with channel length down to 30 nm, contact length down to 13 nm and capacitive effective oxide thickness (CET) down to 1.9 nm. These devices show best-in-class performance with transconductance of 185 μS/μm and a minimum subthreshold swing (SS) of 86 mV/dec. We find that scaling the top-contact length has no impact on the contact resistance and electrostatics of three monolayers MoS2 transistors, because edge injection is dominant. Further, we identify that SS degradation occurs at short channel length and can be mitigated by reducing the CET and lowering the Schottky barrier height. Finally, using a power performance area (PPA) analysis, we present a roadmap of material improvements to make 2D devices competitive with Silicon gate-all-around devices.


2005 ◽  
Vol 11 (4) ◽  
pp. 205-210 ◽  
Author(s):  
Joacim Stalfors ◽  
Ingela Björholt ◽  
Thomas Westin

Multidisciplinary team (MDT) meetings are used for establishing diagnosis, for tumour, node, metastasis (TNM) classification and for treatment in head and neck tumour patients in the western region of Sweden. Because of the distances, telemedicine was introduced to link the regional hospital to two of the three district general hospitals (DGHs). We evaluated the costs of presenting patients face to face (FTF) versus via telemedicine. Cost analyses were based on questionnaires completed by patients presented at the MDT meeting. A total of 39 patients were included in the FTF group and 45 patients in the telemedicine group. The cost analysis showed that FTF presentation cost SEK 2267 versus SEK 2036 by telemedicine (difference not significant). The small difference was explained by the fact that the responsible physician accompanied only six of 39 patients when presented FTF, but when presented via telemedicine the DGH physician always participated. A sensitivity analysis revealed that if the responsible physician always accompanied his/her patient for presentation FTF, the cost would be SEK 5366 per patient. This study shows that costs may be saved by carrying out MDT meetings by means of telemedicine instead of FTF.


Urology ◽  
2018 ◽  
Vol 113 ◽  
pp. 40-44 ◽  
Author(s):  
Vitaly Zholudev ◽  
Ilan J. Safir ◽  
Mark N. Painter ◽  
John A. Petros ◽  
Christopher P. Filson ◽  
...  

2021 ◽  
Author(s):  
Chih-Cheng Chang ◽  
Shao-Tzu Li ◽  
Tong-Lin Pan ◽  
Chia-Ming Tsai ◽  
I-Ting Wang ◽  
...  

Abstract Device quantization of in-memory computing (IMC) that considers the non-negligible variation and finite dynamic range of practical memory technology is investigated, aiming for quantitatively co-optimizing system performance on accuracy, power, and area. Architecture- and algorithm-level solutions are taken into consideration. Weight-separate mapping, VGG-like algorithm, multiple cells per weight, and fine-tuning of the classifier layer are effective for suppressing inference accuracy loss due to variation and allow for the lowest possible weight precision to improve area and energy efficiency. Higher priority should be given to developing low-conductance and low-variability memory devices that are essential for energy and area-efficiency IMC whereas low bit precision (< 3b) and memory window (<10) are less concerned.


Sign in / Sign up

Export Citation Format

Share Document