scholarly journals Impact of device scaling on the electrical properties of MoS2 field-effect transistors

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Goutham Arutchelvan ◽  
Quentin Smets ◽  
Devin Verreck ◽  
Zubair Ahmed ◽  
Abhinav Gaur ◽  
...  
Keyword(s):  
Field Effect Transistors ◽  
Oxide Thickness ◽  
Channel Length ◽  
Contact Length ◽  
Power Performance ◽  
Semiconducting Materials ◽  
Large Area ◽  
Short Channel ◽  
Device Scaling ◽  
Performance Area

AbstractTwo-dimensional semiconducting materials are considered as ideal candidates for ultimate device scaling. However, a systematic study on the performance and variability impact of scaling the different device dimensions is still lacking. Here we investigate the scaling behavior across 1300 devices fabricated on large-area grown MoS2 material with channel length down to 30 nm, contact length down to 13 nm and capacitive effective oxide thickness (CET) down to 1.9 nm. These devices show best-in-class performance with transconductance of 185 μS/μm and a minimum subthreshold swing (SS) of 86 mV/dec. We find that scaling the top-contact length has no impact on the contact resistance and electrostatics of three monolayers MoS2 transistors, because edge injection is dominant. Further, we identify that SS degradation occurs at short channel length and can be mitigated by reducing the CET and lowering the Schottky barrier height. Finally, using a power performance area (PPA) analysis, we present a roadmap of material improvements to make 2D devices competitive with silicon gate-all-around devices.

scholarly journals Impact of Device Scaling on the Electrical Properties of MoS2 Field-effect Transistors

2021 ◽  
Author(s):  
Goutham Arutchelvan ◽  
Quentin Smets ◽  
Devin Verreck ◽  
Zubair Ahmed ◽  
Abhinav Gaur ◽  
...  
Keyword(s):  
Field Effect Transistors ◽  
Oxide Thickness ◽  
Channel Length ◽  
Contact Length ◽  
Power Performance ◽  
Semiconducting Materials ◽  
Large Area ◽  
Short Channel ◽  
Device Scaling ◽  
Performance Area

Abstract Two-dimensional semiconducting materials are considered as ideal candidates for ultimate device scaling. However, a systematic study on the performance and variability impact of scaling the different device dimensions is still lacking. Here we investigate the scaling behavior across 1300 devices fabricated on large-area grown MoS2 material with channel length down to 30 nm, contact length down to 13 nm and capacitive effective oxide thickness (CET) down to 1.9 nm. These devices show best-in-class performance with transconductance of 185 μS/μm and a minimum subthreshold swing (SS) of 86 mV/dec. We find that scaling the top-contact length has no impact on the contact resistance and electrostatics of three monolayers MoS2 transistors, because edge injection is dominant. Further, we identify that SS degradation occurs at short channel length and can be mitigated by reducing the CET and lowering the Schottky barrier height. Finally, using a power performance area (PPA) analysis, we present a roadmap of material improvements to make 2D devices competitive with Silicon gate-all-around devices.

A One-Micrometer Channel Length α-Si Thin-Film Field-Effect Transistor

1984 ◽  
Vol 33 ◽  
Author(s):  
Z. Yaniv ◽  
G. Hansell ◽  
M. Vijan ◽  
V. Cannella
Keyword(s):  
Thin Film ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Liquid Crystal Displays ◽  
Channel Length ◽  
Large Area ◽  
Short Channel ◽  
Threshold Voltages ◽  
Effect Transistor ◽  
Si Thin Film

ABSTRACTA new method of fabricating short channel α-Si TFTs has been developed. One-micrometer channel length α-Si thin-film field effect transistors have been fabricated and tested. Threshold voltages as low as 1.9V and field-effect mobilities as high as 1 cm 2/V-sec are reported. These devices were fabricated by techniques compatible with the production of large area liquid crystal displays.

Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

2017 ◽  
Vol 2 (2) ◽  
pp. 15-19 ◽  
Author(s):  
Md. Saud Al Faisal ◽  
Md. Rokib Hasan ◽  
Marwan Hossain ◽  
Mohammad Saiful Islam
Keyword(s):  
High Speed ◽  
Field Effect Transistors ◽  
Cmos Technology ◽  
Channel Length ◽  
Capacitive Coupling ◽  
Oxide Semiconductor ◽  
Double Gate ◽  
Short Channel ◽  
Channel Effects ◽  
Silvaco Atlas

GaN-based double gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green’s function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, VGS =1 V while it is going to off at VGS = 0 V. The ON-state and OFF-state drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, VDS = 0.75 V. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (LUN). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.

On the DIBL Reduction Effect of Short Channel Carbon Nanotube Field Effect Transistors

2016 ◽  
Vol 6 (4) ◽  
pp. 1514
Author(s):  
Khial Aicha ◽  
Rechem Djamil ◽  
Azizi Chrifa ◽  
Zaabat Mourad
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Liquid Nitrogen Temperature ◽  
Oxide Thickness ◽  
Short Channel ◽  
High K ◽  
Different Temperatures ◽  
Reduction Effect ◽  
High K Materials ◽  
Non Equilibrium Green’S Function

The Drain Induced Barrier Lowering (DIBL), in carbon Nanotubes-Fet (CNTFETS), is a challenging study that still needs investigation. Based on a numerical model, the Non-Equilibrium Green’s Function (NEGF) approach was applied to simulate the DIBL effect in CNTFETS. In this study,  the effect of the length gate ranging from 10 to 30 nm, for different temperatures (77K, 15K, 300K and 400K) on the DIBL was investigated. Then the variation of DIBL effect as a function of the nanotubes diameter varying over the following chiralities: (13, 0), (16, 0), (19, 0), (23, 0) and (25, 0) was undertaken. Afterworlds, we conducted the variation of DIBL impact as a function of the oxide thickness with the values: 1.5 nm, 3 nm, 4.5 nm, 6 nm and 7 nm. Moreover, the DIBL effect was carried at depending upon the high-k materials such as:  SiO_2, HfO_2, ZrO_2, 〖Ta〗_2 O_2 and TiO_2. Finally, a conclusion is made basing at the different findings which revealed that the best reduce of DIBL impact was recorded under a liquid Nitrogen temperature of 77 K.

scholarly journals Comparative Simulation Analysis of Process Parameter Variations in 20 nm Triangular FinFET

2017 ◽  
Vol 2017 ◽  
pp. 1-8 ◽  
Author(s):  
Satyam Shukla ◽  
Sandeep Singh Gill ◽  
Navneet Kaur ◽  
H. S. Jatana ◽  
Varun Nehru
Keyword(s):  
Process Parameters ◽  
Simulation Analysis ◽  
Oxide Thickness ◽  
Channel Length ◽  
Deep Submicron ◽  
Device Structure ◽  
Short Channel ◽  
20 Nm ◽  
The Impact ◽  
Fin Shape

Technology scaling below 22 nm has brought several detrimental effects such as increased short channel effects (SCEs) and leakage currents. In deep submicron technology further scaling in gate length and oxide thickness can be achieved by changing the device structure of MOSFET. For 10–30 nm channel length multigate MOSFETs have been considered as most promising devices and FinFETs are the leading multigate MOSFET devices. Process parameters can be varied to obtain the desired performance of the FinFET device. In this paper, evaluation of on-off current ratio (Ion/Ioff), subthreshold swing (SS) and Drain Induced Barrier Lowering (DIBL) for different process parameters, that is, doping concentration (1015/cm3 to 1018/cm3), oxide thickness (0.5 nm and 1 nm), and fin height (10 nm to 40 nm), has been presented for 20 nm triangular FinFET device. Density gradient model used in design simulation incorporates the considerable quantum effects and provides more practical environment for device simulation. Simulation result shows that fin shape has great impact on FinFET performance and triangular fin shape leads to reduction in leakage current and SCEs. Comparative analysis of simulation results has been investigated to observe the impact of process parameters on the performance of designed FinFET.

scholarly journals Design and Characterization of the Next Generation Nanowire Amplifiers

VLSI Design ◽  
2008 ◽  
Vol 2008 ◽  
pp. 1-5
Author(s):  
Sotoudeh Hamedi-Hagh ◽  
Ahmet Bindal
Keyword(s):  
High Speed ◽  
Field Effect Transistors ◽  
Channel Length ◽  
Next Generation ◽  
Short Channel ◽  
Surrounding Gate ◽  
Channel Effects ◽  
Gate Control ◽  
Voltage Swing

Vertical nanowire surrounding gate field effect transistors (SGFETs) provide full gate control over the channel to eliminate short-channel effects. This paper presents design and characterization of a differential pair amplifier using NMOS and PMOS SGFETs with a 10 nm channel length and a 2 nm channel radius. The amplifier dissipates 5 μW power and provides 5 THz bandwidth with a voltage gain of 16, a linear output voltage swing of 0.5 V, and a distortion better than 3% from a 1.8 V power supply and a 20 aF capacitive load. The 2nd- and 3rd-order harmonic distortions of the amplifier are −40 dBm and −52 dBm, respectively, and the 3rd-order intermodulation is −24 dBm for a two-tone input signal with 10 mV amplitude and 10 GHz frequency spacing. All these parameters indicate that vertical nanowire surrounding gate transistors are promising candidates for the next generation high-speed analog and VLSI technologies.

scholarly journals Threshold voltage roll-off for sub-10 nm asymmetric double gate MOSFET

2019 ◽  
Vol 9 (1) ◽  
pp. 163
Author(s):  
Hakkee Jung
Keyword(s):  
Threshold Voltage ◽  
Tunneling Current ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Channel Length ◽  
Double Gate ◽  
Short Channel ◽  
Double Gate Mosfet ◽  
Channel Effects ◽  
Channel Thickness

Threshold voltage roll-off is analyzed for sub-10 nm asymmetric double gate (DG) MOSFET. Even asymmetric DGMOSFET will increase threshold voltage roll-off in sub-10 nm channel length because of short channel effects due to the increase of tunneling current, and this is an obstacle against the miniaturization of asymmetric DGMOSFET. Since asymmetric DGMOSFET can be produced differently in top and bottom oxide thickness, top and bottom oxide thicknesses will affect the threshold voltage roll-off. To analyze this, <em>thermal</em><em> </em>emission current and tunneling current have been calculated, and threshold voltage roll-off by the reduction of channel length has been analyzed by using channel thickness and top/bottom oxide thickness as parameters. As a result, it is found that, in short channel asymmetric double gate MOSFET, threshold voltage roll-off is changed greatly according to top/bottom gate oxide thickness, and that threshold voltage roll-off is more influenced by silicon thickness. In addition, it is found that top and bottom oxide thickness have a relation of inverse proportion mutually for maintaining identical threshold voltage. Therefore, it is possible to reduce the leakage current of the top gate related with threshold voltage by increasing the thickness of the top gate oxide while maintaining the same threshold voltage.

scholarly journals On the DIBL Reduction Effect of Short Channel Carbon Nanotube Field Effect Transistors

2016 ◽  
Vol 6 (4) ◽  
pp. 1514
Author(s):  
Khial Aicha ◽  
Rechem Djamil ◽  
Azizi Chrifa ◽  
Zaabat Mourad
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Liquid Nitrogen Temperature ◽  
Oxide Thickness ◽  
Short Channel ◽  
High K ◽  
Different Temperatures ◽  
Reduction Effect ◽  
High K Materials ◽  
Non Equilibrium Green’S Function

The Drain Induced Barrier Lowering (DIBL), in carbon Nanotubes-Fet (CNTFETS), is a challenging study that still needs investigation. Based on a numerical model, the Non-Equilibrium Green’s Function (NEGF) approach was applied to simulate the DIBL effect in CNTFETS. In this study,  the effect of the length gate ranging from 10 to 30 nm, for different temperatures (77K, 15K, 300K and 400K) on the DIBL was investigated. Then the variation of DIBL effect as a function of the nanotubes diameter varying over the following chiralities: (13, 0), (16, 0), (19, 0), (23, 0) and (25, 0) was undertaken. Afterworlds, we conducted the variation of DIBL impact as a function of the oxide thickness with the values: 1.5 nm, 3 nm, 4.5 nm, 6 nm and 7 nm. Moreover, the DIBL effect was carried at depending upon the high-k materials such as:  SiO_2, HfO_2, ZrO_2, 〖Ta〗_2 O_2 and TiO_2. Finally, a conclusion is made basing at the different findings which revealed that the best reduce of DIBL impact was recorded under a liquid Nitrogen temperature of 77 K.

Effective Dielectric Thickness Scaling for High-K Gate Dielectric Mosfets

2002 ◽  
Vol 716 ◽  
Author(s):  
Krishna Kumar Bhuwalka ◽  
Nihar R. Mohapatra ◽  
Siva G. Narendra ◽  
V Ramgopal Rao
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Oxide Thickness ◽  
Channel Length ◽  
Short Channel ◽  
Dielectric Thickness ◽  
High K ◽  
Fringing Field ◽  
High K Dielectric ◽  
Physical Thickness

AbstractIt has been shown recently that the short channel performance worsens for high-K dielectric MOSFETs as the physical thickness to the channel length ratio increases, even when the effective oxide thickness (EOT) is kept identical to that of SiO2. In this work we have systematically evaluated the effective dielectric thickness for different Kgate to achieve targeted threshold voltage (Vt), drain-induced barrier lowering (DIBL) and Ion/Ioff ratio for different technology generations down to 50 nm using 2-Dimensional process and device simulations. Our results clearly show that the oxide thickness scaling for high-K gate dielectrics and SiO2 follow different trends and the fringing field effects must be taken into account for estimation of effective dielectric thickness when SiO2 is replaced by a high-K dielectric.

Effect of Channel Profile Engineering on Hot Carrier Reliability in nMOSFETs with 100 nm Channel Lengths

1997 ◽  
Vol 473 ◽  
Author(s):  
Samar K. Saha
Keyword(s):  
Supply Voltage ◽  
High Surface ◽  
Device Simulation ◽  
Oxide Thickness ◽  
Channel Length ◽  
Short Channel ◽  
Hot Carrier ◽  
Hot Carrier Effects ◽  
Doping Profiles ◽  
Substrate Concentrations

ABSTRACTHot-carrier effect was studied for different channel doping profiles in nMOSFET devices with effective channel length near 100 nm using a device simulator. The test structures for device simulation were generated using gate oxide thickness of 3 nm. The channel doping profiles used were abrupt- and graded-retrograde types with low surface and high substrate concentrations, and conventional step profiles with high surface and low substrate concentrations. For accurate device simulation, a hydrodynamic model for semiconductors was used to simulate the non-local transport phenomena in the devices. The simulation results indicate that for ultra-short channel devices, the current drivability and the hot-carrier effects depend on the shape of channel doping profiles. For a given supply voltage, the hot-carrier effects in ultra-short channel devices can be controlled by optimizing the channel doping profiles.

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