TCAD-based characterization of logic cells: Power, performance, area, and variability

Author(s):  
H.W. Karner ◽  
C. Kernstock ◽  
Z. Stanojevic ◽  
O. Baumgartner ◽  
F. Schanovsky ◽  
...  
2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Goutham Arutchelvan ◽  
Quentin Smets ◽  
Devin Verreck ◽  
Zubair Ahmed ◽  
Abhinav Gaur ◽  
...  

AbstractTwo-dimensional semiconducting materials are considered as ideal candidates for ultimate device scaling. However, a systematic study on the performance and variability impact of scaling the different device dimensions is still lacking. Here we investigate the scaling behavior across 1300 devices fabricated on large-area grown MoS2 material with channel length down to 30 nm, contact length down to 13 nm and capacitive effective oxide thickness (CET) down to 1.9 nm. These devices show best-in-class performance with transconductance of 185 μS/μm and a minimum subthreshold swing (SS) of 86 mV/dec. We find that scaling the top-contact length has no impact on the contact resistance and electrostatics of three monolayers MoS2 transistors, because edge injection is dominant. Further, we identify that SS degradation occurs at short channel length and can be mitigated by reducing the CET and lowering the Schottky barrier height. Finally, using a power performance area (PPA) analysis, we present a roadmap of material improvements to make 2D devices competitive with silicon gate-all-around devices.


2019 ◽  
Vol 28 (supp01) ◽  
pp. 1940009
Author(s):  
Aleš Chvála ◽  
Lukáš Nagy ◽  
Juraj Marek ◽  
Juraj Priesol ◽  
Daniel Donoval ◽  
...  

This paper presents monolithic integrated InAlN/GaN NAND and NOR logic cells comprising depletion-mode, enhancement-mode and dual-gate enhancement-mode high electron mobility transistors (HEMTs). The designed NAND and NOR logic cells consist of the depletion-mode and enhancement-mode HEMT transistors integrated onto a single die. InAlN/GaN-based NAND and NOR logic cells with good static and dynamic performance are demonstrated for the first time. Calibrated static and dynamic electrophysical models are proposed for 2D device simulations in Sentaurus Device environment. Sentaurus Device mixed-mode setup interconnects the transistors to NAND and NOR logic circuits which allows analysis and characterization of the devices as a complex system. Circuit models of depletion-mode, enhancement-mode and dual-gate HEMTs are designed and calibrated by experimental results and 2D device simulations. The proposed models exhibit highly accurate results.


Author(s):  
J. Costa ◽  
S. McHugh ◽  
N. Rice ◽  
P. J. Turner ◽  
B. A. Willemsen ◽  
...  
Keyword(s):  

2016 ◽  
Vol 7 (8) ◽  
pp. 1602239 ◽  
Author(s):  
Nicolas Besnard ◽  
Aurélien Etiemble ◽  
Thierry Douillard ◽  
Olivier Dubrunfaut ◽  
Pierre Tran-Van ◽  
...  

Author(s):  
Jim Costa ◽  
Sean McHugh ◽  
Patrick Turner ◽  
Balam Willemsen ◽  
Neal Fenzi ◽  
...  
Keyword(s):  

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