scholarly journals Optimizing HEVC CABAC Decoding with a Context Model Cache and Application-Specific Prefetching

2015 ◽  
Author(s):  
Philipp Habermann ◽  
Chi Ching Chi ◽  
Mauricio Alvarez-Mesa ◽  
Ben Juurlink
Keyword(s):  
Context Model ◽  
Application Specific

Architecture Models to Facilitate Communication of Clinical Information

1999 ◽  
Vol 38 (04/05) ◽  
pp. 326-331
Author(s):  
S. Kay
Keyword(s):  
Health Care ◽  
Clinical Information ◽  
Reference Architecture ◽  
Context Model ◽  
Electronic Health

AbstractThis is an account of the development and use of a context model for facilitating the communication of clinical information. Its function is to articulate the principle of context within a reference architecture for the Electronic Health Care Record (EHCR). The work required a re-examination of established models of communication, the purpose being to use them to support an architecture that could be reasonably expected to accommodate future, and by definition unforeseeable, developments in EHCR communication. The Context Model is built upon seven recognized constituents of communication. These constituents, although having their origin in the engineering of signal communication, have been found to be useful for explication both in the verbal and textual communication of narratives between people. The electronic health care record architecture supported by the model is the European prestandard ENV13606-1.

Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips

2012 ◽  
Vol E95-C (4) ◽  
pp. 534-545 ◽  
Author(s):  
Wei ZHONG ◽  
Takeshi YOSHIMURA ◽  
Bei YU ◽  
Song CHEN ◽  
Sheqin DONG ◽  
...  
Keyword(s):  
Cluster Generation ◽  
Application Specific ◽  
Network Component

The Axis Feature: Illusionary Effects on Children's Judgments of Length

1982 ◽  
Vol 55 (3) ◽  
pp. 720-722
Author(s):  
Anat Scher
Keyword(s):  
Relative Length ◽  
The Other ◽  
Context Model ◽  
Structural Pattern ◽  
Perceptual Judgments ◽  
Length Estimation ◽  
Different Diameters

The effect of the position of lines on length estimation was investigated. 40 5-yr.-olds were asked to compare the two arms of an L-shaped figure presented inside circular frames of different diameters. For each figure one of the arms was on the axis, that is, the diameter, and the other arm was perpendicular to that axis. In making perceptual judgments about the relative length of two lines the children tended to describe the on-axis line as longer than the off-axis line. This illusion which, presumably, reflects a perceptual force induced by the characteristics of the structural pattern, supports the context model of visual anomalies.

Efficient Computing in Image Processing and DSPs with ASIP Based Multiplier

2019 ◽  
Vol 13 (2) ◽  
pp. 174-180
Author(s):  
Poonam Sharma ◽  
Ashwani Kumar Dubey ◽  
Ayush Goyal
Keyword(s):  
Image Processing ◽  
High Speed ◽  
Computation Time ◽  
Digital Signal ◽  
Instruction Set ◽  
Computationally Efficient ◽  
Specific Instruction ◽  
Processor Core ◽  
Speed Performance ◽  
Application Specific

Background: With the growing demand of image processing and the use of Digital Signal Processors (DSP), the efficiency of the Multipliers and Accumulators has become a bottleneck to get through. We revised a few patents on an Application Specific Instruction Set Processor (ASIP), where the design considerations are proposed for application-specific computing in an efficient way to enhance the throughput. Objective: The study aims to develop and analyze a computationally efficient method to optimize the speed performance of MAC. Methods: The work presented here proposes the design of an Application Specific Instruction Set Processor, exploiting a Multiplier Accumulator integrated as the dedicated hardware. This MAC is optimized for high-speed performance and is the application-specific part of the processor; here it can be the DSP block of an image processor while a 16-bit Reduced Instruction Set Computer (RISC) processor core gives the flexibility to the design for any computing. The design was emulated on a Xilinx Field Programmable Gate Array (FPGA) and tested for various real-time computing. Results: The synthesis of the hardware logic on FPGA tools gave the operating frequencies of the legacy methods and the proposed method, the simulation of the logic verified the functionality. Conclusion: With the proposed method, a significant improvement of 16% increase in throughput has been observed for 256 steps iterations of multiplier and accumulators on an 8-bit sample data. Such an improvement can help in reducing the computation time in many digital signal processing applications where multiplication and addition are done iteratively.

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