Cost-effective optimization of serial link system for Signal Integrity and Power Integrity

2011 ◽  
Author(s):  
Raj Kumar Nagpal ◽  
Jai Narayan Tripathi ◽  
Rakesh Malik
Keyword(s):  
Signal Integrity ◽  
Cost Effective ◽  
Power Integrity ◽  
Serial Link

Signal Integrity Analysis for RF System-in-Package

2011 ◽  
Author(s):  
Jeff Chen ◽  
Weiping Li ◽  
Feng Ling
Keyword(s):  
Design Methodology ◽  
Electromagnetic Compatibility ◽  
Signal Integrity ◽  
Power Integrity ◽  
Rf System ◽  
Noise Coupling ◽  
Design Time ◽  
Close Proximity ◽  
First Pass ◽  
Integrity Analysis

RF System-in-Package (SiP) has become a viable packaging platform, which offers great flexibility to integrate ICs with different processes and different architects. With operating frequency becoming higher and multiple available technologies embedded in one package, the system could fail due to the undesired noise coupling resulted from the close proximity of the components. Therefore, the design methodology with signal integrity (SI), power integrity (PI), and electromagnetic compatibility (EMC) analysis becomes essential to tackle the SiP integration issues. The paper presents a RF SiP design methodology with SI/PI/EMC simulations, which greatly reduces the design time and enables first-pass success.

Integral Equation Technique for the Simulation of Signal Integrity and Power Integrity

Frequenz ◽  
2011 ◽  
Vol 65 (9-10) ◽  
Author(s):  
Xing-Chang Wei ◽  
De-Cao Yang ◽  
Er-Ping Li
Keyword(s):  
Integral Equation ◽  
Signal Integrity ◽  
Power Integrity

SerDes Design and Modeling over 25+ Gb/s Serial Link

2011 ◽  
Vol 2011 (1) ◽  
pp. 000044-000060
Author(s):  
Pervez M. Aziz ◽  
Adam Healey ◽  
Cathy Liu ◽  
Freeman Zhong ◽  
Alex Zabroda
Keyword(s):  
High Speed ◽  
Forward Error Correction ◽  
Circuit Simulation ◽  
Signal Integrity ◽  
Systems Modeling ◽  
Behavioral Models ◽  
Noisy Environments ◽  
Serial Link ◽  
Link Performance ◽  
Forward Error

In this paper, signal integrity challenges for high speed serial link at 25 Gb/s, such as lossy channels and noisy environments are discussed. A few solution spaces to address those challenges are investigated, such as advanced equalization schemes, alternative signaling formats and forward error correction. It demonstrates that advanced signal processing enables long reach and extra long reach serial link performance at 25 Gb/s in next generation systems. Modeling methodologies used in SerDes behavioral models to ensure good correlation with transistor level circuit simulation are also discussed.

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