Design and experimental verification of on-chip signal integrity analyzer (OSIA) scheme for eye diagram monitoring of a high-speed serial link

Author(s):  
Minchul Shin ◽  
Myunghoi Kim ◽  
Kyoungchoul Koo ◽  
Sunkyu Kong ◽  
Joungho Kim
Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 766
Author(s):  
Hao Lv ◽  
Shengbing Zhang ◽  
Wei Han ◽  
Yongqiang Liu ◽  
Shuo Liu ◽  
...  

In recent years, microelectronics technology has entered the era of nanoelectronics/integrated microsystems. System in Package (SiP) and System on Chip (SoC) are two important technical approaches for microsystems. The development of micro-system technology has made it possible to miniaturize airborne and missile-borne electronic equipment. This paper introduces the design and implementation of an aerospace miniaturized computer system. The SiP chip uses Xilinx Zynq® SoC (2ARM® + FPGA), FLASH memory and DDR3 memory as the main components, and integrates with SiP high-density system packaging technology. The chip has the advantages of small size and ultra-low power consumption compared with the traditional PCB circuit design. A pure software-based DDR3 signal eye diagram test method is used to verify the improvement inf the signal integrity of the chip without the need for probe measurement. The method of increasing the thermal conductive silver glue was used to improve the thermal performance after the test and analysis. The SiP chip was tested and analyzed with other mainstream aviation computers using a heading measurement of extended Kalman filter (EKF) algorithm. The paper has certain reference value and research significance in the miniaturization of the aviation computer system, the heat dissipation technology of SiP chip and the test method of signal integrity.


2015 ◽  
Vol 661 ◽  
pp. 121-127 ◽  
Author(s):  
Yeong Lin Lai ◽  
Wen Jung Chiang

The system in a package (SiP) including of a system on a chip (SoC) and a double-data-rate-three synchronous dynamic random access memory (DDR3 SDRAM) were studied with respect to the high-speed characteristics. The SiP was the multi-chip-module thin-profile fine-pitch ball grid array (MCM TFBGA) package with four-layer substrate. The high-speed 1600-Mbps data rate DDR3 signals were used in the signal integrity (SI) analysis. The SiP with low-cost silver (Ag) wires displayed a 500.18-ps aperture width in the eye diagram, which was successfully achieved signal integrity (SI) performance requirement. This work demonstrated the SiP with the Ag wires was the great potential solution for the advanced high-speed product applications.


2011 ◽  
Vol 2011 (1) ◽  
pp. 000044-000060
Author(s):  
Pervez M. Aziz ◽  
Adam Healey ◽  
Cathy Liu ◽  
Freeman Zhong ◽  
Alex Zabroda

In this paper, signal integrity challenges for high speed serial link at 25 Gb/s, such as lossy channels and noisy environments are discussed. A few solution spaces to address those challenges are investigated, such as advanced equalization schemes, alternative signaling formats and forward error correction. It demonstrates that advanced signal processing enables long reach and extra long reach serial link performance at 25 Gb/s in next generation systems. Modeling methodologies used in SerDes behavioral models to ensure good correlation with transistor level circuit simulation are also discussed.


1999 ◽  
Vol 6 (10-12) ◽  
pp. 823-828 ◽  
Author(s):  
Y Hashimoto ◽  
S Yorozu ◽  
H Numata ◽  
M Koike ◽  
M Tanaka ◽  
...  

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