Differential Power Analysis (DPA) attacks are known as viable and practical techniques to break the security of cryptographic algorithms. In this type of attack, an adversary extracts the encryption key based on the correlation of consumed power of the hardware running encryption algorithms to the processed data. To address DPA attacks in the hardware layer, various techniques have been proposed thus far. However, current techniques generally impose high performance overhead. Especially, the power overhead is a serious issue which may limit the applicability of current techniques in power-constrained applications. In this paper, combinational counters are explored as a way to address the DPA attacks. By randomizing the consumed power in each clock cycle of the circuit operation, these counters can enhance the resistance of the cryptographic cores against DPA attacks with low power overhead as well as zero timing overhead. Experimental results for an AES S-Box module in 45[Formula: see text]nm technology reveal that the proposed technique is capable of achieving higher level of security in comparison to two other approaches while preserving the power and performance overhead at a same or lower level.
Design of Power Efficient 32-Bit Processing Unit
