A double-width algorithmic balancing to prevent power analysis Side Channel Attacks in AES

2013 ◽  
Author(s):  
Ankita Arora ◽  
Jude Angelo Ambrose ◽  
Jorgen Peddersen ◽  
Sri Parameswaran
Keyword(s):  
Power Analysis ◽  
Side Channel ◽  
Side Channel Attacks

scholarly journals Side-Channel Power Resistance for Encryption Algorithms Using Implementation Diversity

Cryptography ◽  
2020 ◽  
Vol 4 (2) ◽  
pp. 13
Author(s):  
Ivan Bow ◽  
Nahome Bete ◽  
Fareena Saqib ◽  
Wenjie Che ◽  
Chintan Patel ◽  
...  
Keyword(s):  
Power Analysis ◽  
Side Channel ◽  
Side Channel Attacks ◽  
Dynamic Partial Reconfiguration ◽  
Channel Power ◽  
Diversity Techniques ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Encryption Algorithms

This paper investigates countermeasures to side-channel attacks. A dynamic partial reconfiguration (DPR) method is proposed for field programmable gate arrays (FPGAs)s to make techniques such as differential power analysis (DPA) and correlation power analysis (CPA) difficult and ineffective. We call the technique side-channel power resistance for encryption algorithms using DPR, or SPREAD. SPREAD is designed to reduce cryptographic key related signal correlations in power supply transients by changing components of the hardware implementation on-the-fly using DPR. Replicated primitives within the advanced encryption standard (AES) algorithm, in particular, the substitution-box (SBOX)s, are synthesized to multiple and distinct gate-level implementations. The different implementations change the delay characteristics of the SBOXs, reducing correlations in the power traces, which, in turn, increases the difficulty of side-channel attacks. The effectiveness of the proposed countermeasures depends greatly on this principle; therefore, the focus of this paper is on the evaluation of implementation diversity techniques.

scholarly journals The Design of Compact SM4 Encryption and Decryption Circuits That Are Resistant to Bypass Attack

Electronics ◽  
2020 ◽  
Vol 9 (7) ◽  
pp. 1102
Author(s):  
Fang Zhou ◽  
Benjun Zhang ◽  
Ning Wu ◽  
Xiangli Bu
Keyword(s):  
Linear Transformation ◽  
Power Analysis ◽  
Side Channel ◽  
Random Delay ◽  
Side Channel Attacks ◽  
Differential Power Analysis ◽  
Operation Method ◽  
Encryption And Decryption ◽  
Power Curves ◽  
Random Insertion

In order to achieve the purpose of defending against side channel attacks, a compact SM4 circuit was designed based on the mask and random delay technique, and the linear transformation module was designed with random insertion of the pseudo operation method. By analyzing the glitch data generated by the S-box of SM4 with different inputs, the security against glitch attacks was confirmed. Then, the DPA (Differential Power Analysis) was performed on the designed circuit. The key could not be successfully obtained even in the case of 100,000 power curves, so that the safety of SM4 against DPA is verified. Finally, using Synopsys DC (Design Compiler, Mountain View, CA94043DC, USA) to synthesize the designed circuit, the results show that the area of the designed circuit in the SMIC 0.18 process is 82,734 μm2, which is 48% smaller than results reported in other papers.

Advanced modes in AES: Are they safe from power analysis based side channel attacks?

2014 ◽  
Author(s):  
Darshana Jayasinghe ◽  
Roshan Ragel ◽  
Jude Angelo Ambrose ◽  
Aleksandar Ignjatovic ◽  
Sri Parameswaran
Keyword(s):  
Power Analysis ◽  
Side Channel ◽  
Side Channel Attacks

scholarly journals An Efficient Correlation Power Analysis Attack Using Variational Mode Decomposition 

2020 ◽  
Vol 31 (1) ◽  
pp. 17-25
Keyword(s):  
Power Analysis ◽  
Side Channel ◽  
Variational Mode Decomposition ◽  
Secret Key ◽  
Intrinsic Mode Functions ◽  
Side Channel Attacks ◽  
Mode Decomposition ◽  
Noisy Conditions ◽  
Correlation Power Analysis ◽  
Evaluation Board

Side channel attacks (SCAs) are now a real threat to cryptographic devices and correlation power analysis (CPA) is the most powerful attack. So far, a CPA attack usually exploits the leakage information from raw power consumption traces that collected from the attack device. In real attack scenarios, these traces collected from measurement equipment are usually contaminated by noise resulting in a decrease in attack efficiency. In this paper, we propose a variant CPA attack that exploits the leakage information from intrinsic mode functions (IMFs) of the power traces. These IMFs are the results of the variational mode decomposition (VMD) process on the raw power traces. This attack technique decreases the number of power traces for correctly recovering the secret key by approximately 13% in normal conditions and 60% in noisy conditions compared to a traditional CPA attack. Experiments were performed on power traces of AES-128 implemented in both microcontroller and FPGA by Sakura-G/W side channel evaluation board to verify the effectiveness of our method.

scholarly journals Novel Side-Channel Attacks on Quasi-Cyclic Code-Based Cryptography

2019 ◽  
pp. 180-212 ◽  
Author(s):  
Bo-Yeon Sim ◽  
Jihoon Kwon ◽  
Kyu Young Choi ◽  
Jihoon Cho ◽  
Aesun Park ◽  
...  
Keyword(s):  
Power Consumption ◽  
Power Analysis ◽  
Cyclic Code ◽  
Linear Equations ◽  
Constant Time ◽  
Side Channel ◽  
Parity Check ◽  
Side Channel Attacks ◽  
Timing Attacks ◽  
Code Based Cryptography

Chou suggested a constant-time implementation for quasi-cyclic moderatedensity parity-check (QC-MDPC) code-based cryptography to mitigate timing attacks at CHES 2016. This countermeasure was later found to become vulnerable to a differential power analysis (DPA) in private syndrome computation, as described by Rossi et al. at CHES 2017. The proposed DPA, however, still could not completely recover accurate secret indices, requiring further solving linear equations to obtain entire secret information. In this paper, we propose a multiple-trace attack which enables to completely recover accurate secret indices. We further propose a singletrace attack which can even work when using ephemeral keys or applying Rossi et al.’s DPA countermeasures. Our experiments show that the BIKE and LEDAcrypt may become vulnerable to our proposed attacks. The experiments are conducted using power consumption traces measured from ChipWhisperer-Lite XMEGA (8-bit processor) and ChipWhisperer UFO STM32F3 (32-bit processor) target boards.

scholarly journals Secure Triple Track Logic Robustness Against Differential Power and Electromagnetic Analyses

2009 ◽  
Vol 4 (1) ◽  
pp. 20-28
Author(s):  
V. Lomné ◽  
A. Dehbaoui ◽  
T. Ordas ◽  
P. Maurine ◽  
L. Torres ◽  
...  
Keyword(s):  
Power Analysis ◽  
Design Guidelines ◽  
Side Channel ◽  
Side Channel Attacks ◽  
Secret Data ◽  
Differential Power Analysis ◽  
Basic Concepts

Side channel attacks (SCA) are known to be efficient techniques to retrieve secret data. In this context, this paper concerns the evaluation of the robustness of secure triple track logic (STTL) against power and electromagnetic analyses on FPGA devices. More precisely, it aims at demonstrating that the basic concepts behind STTL are valid in general and particularly for FPGAs. Also, the paper shows that this new logic may provide interesting design guidelines to get circuits that are resistant to differential power analysis (DPA) attacks which and also more robust against differential electromagnetic attacks (DEMA).

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