A Low-Cost and High-Performance Embedded System Architecture and an Evaluation Methodology

2014 ◽  
Author(s):  
Xiaokun Yang ◽  
Jean H. Andrian
Keyword(s):  
Embedded System ◽  
System Architecture ◽  
High Performance ◽  
Low Cost ◽  
Evaluation Methodology

SiP(System in Package) Solutions with Wafer Level Packaging Technology

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 002226-002253 ◽  
Author(s):  
In Soo Kang ◽  
Jong Heon (Jay) Kim
Keyword(s):  
Embedded System ◽  
High Performance ◽  
Low Cost ◽  
Wafer Level ◽  
Molding Compound ◽  
Wafer Level Packaging ◽  
Ic Packaging ◽  
Chip Size ◽  
Bonding Technology ◽  
Small Form Factor

In mobile application, the WLP technology has been developing to make whole package size almost same as chip size. However, the I/O per chip unit area has increased so that it gets difficult to realize ideal pad pitch for better reliability. Recently, to achieve the thin and small size, high performance and low cost semiconductor package, Embedding Die and Fanout Technologies have been suggested and developed based on wafer level processing. In this work, as a solution of system in package, wafer level embedded package and fanout technology will be reviewed. Firstly, Wafer level embedded System in Package (WL-eSiP) which has daughter chip (small chip) embedded inside mother chip (bigger chip) without any special substrate has been suggested and developed. To realize wafer level embedded system in package (WL-eSiP), wafer level based new processes like wafer level molding for underfilling and encapsulation by molding compound without any special substrate have been applied and developed, including high aspect ratio Cu bumping, mold thinning and chip-to-wafer flipchip bonding. Secondly, Fan-out Package is considered as alternative package structure which means merged package structure of WLCSP (wafer level chip size package) and PCB process. We can make IC packaging widen area for SIP(System in Package) or 3D package. In addition, TSV and IPD are key enabling technology to meet market demands because TSV interconnection can provide wider bandwidth and high transmission speed due to vertical one compared to wire bonding technology and IPD can provide higher performance, more area saving to be assembled and small form factor compared to discrete passive components.

scholarly journals LabVIEW and Open Embedded System

2021 ◽  
Author(s):  
Trinh Quang Duc
Keyword(s):  
User Interface ◽  
Embedded System ◽  
Interface Design ◽  
High Performance ◽  
Low Cost ◽  
User Interface Design ◽  
Development Environment ◽  
Cost System ◽  
National Instrument ◽  
The Embedded System

In this chapter, discussions about the applications based on LabVIEW with a typical open embedded system such as Arduino. Instead of the applications with use of National Instrument hardware, an user can build an low-cost microcontroller-based system which user interface and procedure designed in LabVIEW. Recently, Arduino-based applications are one of interested developments, the embedded system is designed with the low-cost microcontroller of ATMEGA2560 and easy to program with IDE (Interface Development Environment). However, the difficulties of Arduino-based applications are user interface design while LabVIEW is an excellent utilities for the panel designs. The limitation of some LabVIEW applications is the requirements from combination with high performance NI hardwares. Under interactions between LabVIEW and IDE library designed by Arduino, the low-cost system can be easily built for experiments or prototype designs.

scholarly journals An Embedded System for applying High Performance Computing in Educational Learning Activity

2016 ◽  
Vol 4 (1) ◽  
Author(s):  
Irene Erlyn Wina Rachmawan ◽  
Nurul Fahmi ◽  
Edi Wahyu Widodo ◽  
Samsul Huda ◽  
M. Unggul Pamenang ◽  
...  
Keyword(s):  
Embedded System ◽  
High Performance Computing ◽  
High Performance ◽  
Cluster Computing ◽  
Low Cost ◽  
Learning Activity ◽  
Learning Satisfaction ◽  
Parallel Case ◽  
High Performance Computing Cluster ◽  
Performance Computing

HPC (High Performance Computing) has become more popular in the last few years. With the benefits on high computational power, HPC has impact on industry, scientific research and educational activities. Implementing HPC as a curriculum in universities could be consuming a lot of resources because well-known HPC system are using Personal Computer or Server. By using PC as the practical moduls it is need great resources and spaces.  This paper presents an innovative high performance computing cluster system to support education learning activities in HPC course with small size, low cost, and yet powerful enough. In recent years, High Performance computing usually implanted in cluster computing and require high specification computer and expensive cost. It is not efficient applying High Performance Computing in Educational research activiry such as learning in Class. Therefore, our proposed system is created with inexpensive component by using Embedded System to make High Performance Computing applicable for leaning in the class. Students involved in the construction of embedded system, built clusters from basic embedded and network components, do benchmark performance, and implement simple parallel case using the cluster.  In this research we performed evaluation of embedded systems comparing with i5 PC, the results of our embedded system performance of NAS benchmark are similar with i5 PCs. We also conducted surveys about student learning satisfaction that with embedded system students are able to learn about HPC from building the system until making an application that use HPC system.

scholarly journals Energy-Efficient Architecture for CNNs Inference on Heterogeneous FPGA

2019 ◽  
Vol 10 (1) ◽  
pp. 1 ◽  
Author(s):  
Fanny Spagnolo ◽  
Stefania Perri ◽  
Fabio Frustaci ◽  
Pasquale Corsonello
Keyword(s):  
Neural Networks ◽  
Embedded System ◽  
Convolutional Neural Networks ◽  
Energy Efficient ◽  
Power Efficiency ◽  
High Performance ◽  
Large Scale ◽  
Low Cost ◽  
Frame Rate ◽  
Field Programmable

Due to the huge requirements in terms of both computational and memory capabilities, implementing energy-efficient and high-performance Convolutional Neural Networks (CNNs) by exploiting embedded systems still represents a major challenge for hardware designers. This paper presents the complete design of a heterogeneous embedded system realized by using a Field-Programmable Gate Array Systems-on-Chip (SoC) and suitable to accelerate the inference of Convolutional Neural Networks in power-constrained environments, such as those related to IoT applications. The proposed architecture is validated through its exploitation in large-scale CNNs on low-cost devices. The prototype realized on a Zynq XC7Z045 device achieves a power efficiency up to 135 Gops/W. When the VGG-16 model is inferred, a frame rate up to 11.8 fps is reached.

NanoCube: A Low-Cost, Modular, and High-Performance Embedded System for Adaptive Fabrication and Characterization of Nanogaps

2014 ◽  
Vol 13 (2) ◽  
pp. 322-334 ◽  
Author(s):  
Paolo Motto ◽  
Marco Crepaldi ◽  
Gianluca Piccinini ◽  
Danilo Demarchi
Keyword(s):  
Embedded System ◽  
High Performance ◽  
Low Cost ◽  
Fabrication And Characterization

High-Performance and Low-Cost Optical Interconnects.

1995 ◽  
Author(s):  
John A. Neff ◽  
Charles Stirk
Keyword(s):  
Optical Interconnects ◽  
High Performance ◽  
Low Cost

Comparison of UV- and Derivative-Spectrophotometric and HPTLC UVDensitometric Methods for the Determination of Amrinone and Milrinone in Bulk Drugs

2020 ◽  
Vol 16 (3) ◽  
pp. 246-253
Author(s):  
Marcin Gackowski ◽  
Marcin Koba ◽  
Stefan Kruszewski
Keyword(s):  
Thin Layer ◽  
Thin Layer Chromatography ◽  
High Performance ◽  
Low Cost ◽  
Uv Spectra ◽  
Derivative Spectrophotometry ◽  
Therapeutic Monitoring ◽  
Bulk Drug ◽  
Layer Chromatography ◽  
Standard Solutions

Background: Spectrophotometry and thin layer chromatography have been commonly applied in pharmaceutical analysis for many years due to low cost, simplicity and short time of execution. Moreover, the latest modifications including automation of those methods have made them very effective and easy to perform, therefore, the new UV- and derivative spectrophotometry as well as high performance thin layer chromatography UV-densitometric (HPTLC) methods for the routine estimation of amrinone and milrinone in pharmaceutical formulation have been developed and compared in this work since European Pharmacopoeia 9.0 has yet incorporated in an analytical monograph a method for quantification of those compounds. Methods: For the first method the best conditions for quantification were achieved by measuring the lengths between two extrema (peak-to-peak amplitudes) 252 and 277 nm in UV spectra of standard solutions of amrinone and a signal at 288 nm of the first derivative spectra of standard solutions of milrinone. The linearity between D252-277 signal and concentration of amironone and 1D288 signal of milrinone in the same range of 5.0-25.0 μg ml/ml in DMSO:methanol (1:3 v/v) solutions presents the square correlation coefficient (r2) of 0,9997 and 0.9991, respectively. The second method was founded on HPTLC on silica plates, 1,4-dioxane:hexane (100:1.5) as a mobile phase and densitometric scanning at 252 nm for amrinone and at 271 nm for milrinone. Results: The assays were linear over the concentration range of 0,25-5.0 μg per spot (r2=0,9959) and 0,25-10.0 μg per spot (r2=0,9970) for amrinone and milrinone, respectively. The mean recoveries percentage were 99.81 and 100,34 for amrinone as well as 99,58 and 99.46 for milrinone, obtained with spectrophotometry and HPTLC, respectively. Conclusion: The comparison between two elaborated methods leads to the conclusion that UV and derivative spectrophotometry is more precise and gives better recovery, and that is why it should be applied for routine estimation of amrinone and milrinone in bulk drug, pharmaceutical forms and for therapeutic monitoring of the drug.

Low cost and high performance fibre in-line bi-directional optical subassembly for fibre-to-the-home

2007 ◽  
Author(s):  
Hyunseo Kang ◽  
Jong Jin Lee ◽  
Kwonseob Lim ◽  
Seihyoung Lee ◽  
Shinyoung Yoon ◽  
...  
Keyword(s):  
High Performance ◽  
Low Cost ◽  
High Performance Fibre
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