VHDL Implementation of High-Performance and Dynamically Configures Multi-port Cache Memory

Author(s):  
Hassan Bajwa ◽  
Isaac Macwan ◽  
Vignesh Veerapandian ◽  
Xinghao Chen
Author(s):  
Tati Erlina ◽  
Rahmi Eka Putri

Menciptakan komputer yang berkinerja tinggi dan mengkonsumsi daya minimal merupakan salah satu fokus yang menjadi tren penelitian dalam bidang arsitektur komputer belakangan ini. Diketahui bahwa sejumlah faktor berpengaruh dalam menentukan kinerja dan konsumsi daya dari setiap elemen pembangun komputer dan pada akhirnya mempengaruhi kinerja dan konsumsi daya sebuah komputer secara keseluruhan. Fokus penelitian ini adalah untuk mengetahui seberapa besar pengaruh dari fungsi pemetaan (mapping techniques) sebagai salah satu jenis elemen perancangan yang diterapkan pada sebuah cache memory terhadap kinerja dan konsumsi daya dari cache memory dengan mensimulasikannya pada SMPCache dengan berbagai macam benchmark dan CACTI.[En]Creating high performance computers which consume minimal power is one of the focus and has become the trend of research in the field of computer architecture lately. It has been known that a number of factors influence the determination of the performance and power consumption of each of the building elements of the computer and ultimately affect the performance and overall power consumption of a computer. The focus of this research is to find out how much mapping functions as one of the type of design elements applied to a cache memory influence the performance and power consumption of the cache memory by simulating various configuration elements of the design in SMPCache with various benchmarks and CACTI.


Author(s):  
Susumu Takeda ◽  
Hiroki Noguchi ◽  
Kumiko Nomura ◽  
Shinobu Fujita ◽  
Shinobu Miwa ◽  
...  

1995 ◽  
Vol 4 (2) ◽  
pp. 53-58 ◽  
Author(s):  
David H. Bailey

An important issue in obtaining high performance on a scientific application running on a cache-based computer system is the behavior of the cache when data are accessed at a constant stride. Others who have discussed this issue have noted an odd phenomenon in such situations: A few particular innocent-looking strides result in sharply reduced cache efficiency. In this article, this problem is analyzed, and a simple formula is presented that accurately gives the cache efficiency for various cache parameters and data strides.


Author(s):  
Matheus S Serpa ◽  
Eduardo HM Cruz ◽  
Matthias Diener ◽  
Arthur M Krause ◽  
Philippe OA Navaux ◽  
...  

Many software mechanisms for geophysics exploration in oil and gas industries are based on wave propagation simulation. To perform such simulations, state-of-the-art high-performance computing architectures are employed, generating results faster with more accuracy at each generation. The software must evolve to support the new features of each design to keep performance scaling. Furthermore, it is important to understand the impact of each change applied to the software to improve the performance as most as possible. In this article, we propose several optimization strategies for a wave propagation model for six architectures: Intel Broadwell, Intel Haswell, Intel Knights Landing, Intel Knights Corner, NVIDIA Pascal, and NVIDIA Kepler. We focus on improving the cache memory usage, vectorization, load balancing, portability, and locality in the memory hierarchy. We analyze the hardware impact of the optimizations, providing insights of how each strategy can improve the performance. The results show that NVIDIA Pascal outperforms the other considered architectures by up to 8.5[Formula: see text].


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