Assessing Power Efficiency and Performance in Nanosatellite Onboard Computer for Control Applications

2020 ◽  
Vol 1 (2) ◽  
pp. 110-116 ◽  
Author(s):  
Ana Carolina Cabral Pimentel de Melo ◽  
Daniel Chaves Cafe ◽  
Renato Alves Borges
Keyword(s):  
Power Efficiency ◽  
Control Applications ◽  
Onboard Computer ◽  
And Performance

A Low-Cost Electronic Method for Measuring Thyristor Convertor Output

1984 ◽  
Vol 21 (1) ◽  
pp. 75-83
Author(s):  
S. K. Tso ◽  
P. T. Ho
Keyword(s):  
Feedback Control ◽  
Low Cost ◽  
Design Concept ◽  
Control Applications ◽  
Operating Range ◽  
Electronic Method ◽  
And Performance

A low-cost opto-electronic method of measuring convertor output currents is proposed serving to overcome the inherent non-linearity of the simple opto-coupler. The design concept and performance of a laboratory-built transducer are described. Over the full operating range much reduced distortion is achieved. The method is useful for feedback control applications.

scholarly journals “RF-SoC”: Integration Trends of On-Chip CMOS Power Amplifier: Benefits of External PA versus Integrated PA for Portable Wireless Communications

2010 ◽  
Vol 2010 ◽  
pp. 1-7 ◽  
Author(s):  
D. Y. C. Lie
Keyword(s):  
Power Efficiency ◽  
Rf Power Amplifiers ◽  
Rf Power ◽  
Single Chip ◽  
Time To Market ◽  
Higher Power ◽  
System On A Chip ◽  
Design Tradeoffs ◽  
And Performance ◽  
On Chip

RFIC integration has seen dramatic progress since the early 1990s. For example, Si-based single-chip products for GSM, WLAN, Bluetooth, and DECT applications have become commercially available. However, RF power amplifiers (PAs) and switches tend to remain off-chip in the context of single-chip CMOS/BiCMOS transceiver ICs for handset applications. More recently, several WLAN/Bluetooth vendors have successfully integrated less demanding PAs onto the transceivers. This paper will focus on single-chip RF-system-on-a-chip (i.e., “RF-SoC”) implementations that include a high-power PA. An analysis of all tradeoffs inherent to integrating higher power PAs is provided. The analysis includes the development cost, time-to-market, power efficiency, yield, reliability, and performance issues. Recent design trends on highly integrated CMOS WiFi transceivers in the literature will be briefly reviewed with emphasis on the RF-SoC product design tradeoffs impacted by the choice between integrated versus external PAs.

scholarly journals iDirac: a field-portable instrument for long-term autonomous measurements of isoprene and selected VOCs

2020 ◽  
Vol 13 (2) ◽  
pp. 821-838 ◽  
Author(s):  
Conor G. Bolas ◽  
Valerio Ferracci ◽  
Andrew D. Robinson ◽  
Mohammed I. Mead ◽  
Mohd Shahrul Mohd Nadzir ◽  
...  
Keyword(s):  
Power Efficiency ◽  
Modular Design ◽  
Limit Of Detection ◽  
The Novel ◽  
Relative Standard ◽  
New Instrument ◽  
Instrument Control ◽  
Gas Consumption ◽  
And Performance ◽  
Dual Column

Abstract. The iDirac is a new instrument to measure selected hydrocarbons in the remote atmosphere. A robust design is central to its specifications, with portability, power efficiency, low gas consumption and autonomy as the other driving factors in the instrument development. The iDirac is a dual-column isothermal oven gas chromatograph with photoionisation detection (GC-PID). The instrument is designed and built in-house. It features a modular design, with the novel use of open-source technology for accurate instrument control. Currently configured to measure biogenic isoprene, the system is suitable for a range of compounds. For isoprene measurements in the field, the instrument precision (relative standard deviation) is ±10 %, with a limit of detection down to 38 pmol mol−1 (or ppt). The instrument was first tested in the field in 2015 during a ground-based campaign, and has since shown itself suitable for deployment in a variety of environments and platforms. This paper describes the instrument design, operation and performance based on laboratory tests in a controlled environment as well as during deployments in forests in Malaysian Borneo and central England.

Dual Die Package Design Strategy and Performance

2005 ◽  
Author(s):  
Mahadevan Suryakumar ◽  
Lu-Vong T. Phan ◽  
Mathew Ma ◽  
Wajahat Ahmed
Keyword(s):  
Power Efficiency ◽  
High Speed ◽  
High Performance ◽  
Clock Cycle ◽  
Average Power ◽  
Cost Effective ◽  
Design Strategy ◽  
Leakage Power ◽  
Memory Accesses ◽  
And Performance

The alarming growth of power increase has presented numerous packaging challenges for high performance processors. The average power consumed by a processor is the sum of dynamic and leakage power. The dynamic power is proportional to V^2, while the leakage current (therefore leakage power) is proportional to V^b where V is the voltage and b>1 for modern processes. This means lowering voltage reduces energy consumed per clock cycle but reduces the maximum frequency at which the processor can operate at. Since reducing voltage reduces power faster than it does frequency, integrating more cores into the processor would result in better performance/power efficiency but would generate more memory accesses, driving a need for larger cache and high speed signaling [1]. In addition, the design goal to create unified package pinout for both single core and multicore product flavors adds additional constraint to create a cost effective package solution for both market segments. This paper discusses the design strategy and performance of dual die package to optimize package performance for cost.

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