scholarly journals “RF-SoC”: Integration Trends of On-Chip CMOS Power Amplifier: Benefits of External PA versus Integrated PA for Portable Wireless Communications

2010 ◽  
Vol 2010 ◽  
pp. 1-7 ◽  
Author(s):  
D. Y. C. Lie
Keyword(s):  
Power Efficiency ◽  
Rf Power Amplifiers ◽  
Rf Power ◽  
Single Chip ◽  
Time To Market ◽  
Higher Power ◽  
System On A Chip ◽  
Design Tradeoffs ◽  
And Performance ◽  
On Chip

RFIC integration has seen dramatic progress since the early 1990s. For example, Si-based single-chip products for GSM, WLAN, Bluetooth, and DECT applications have become commercially available. However, RF power amplifiers (PAs) and switches tend to remain off-chip in the context of single-chip CMOS/BiCMOS transceiver ICs for handset applications. More recently, several WLAN/Bluetooth vendors have successfully integrated less demanding PAs onto the transceivers. This paper will focus on single-chip RF-system-on-a-chip (i.e., “RF-SoC”) implementations that include a high-power PA. An analysis of all tradeoffs inherent to integrating higher power PAs is provided. The analysis includes the development cost, time-to-market, power efficiency, yield, reliability, and performance issues. Recent design trends on highly integrated CMOS WiFi transceivers in the literature will be briefly reviewed with emphasis on the RF-SoC product design tradeoffs impacted by the choice between integrated versus external PAs.

scholarly journals An overview of on-chip buses

2006 ◽  
Vol 19 (3) ◽  
pp. 405-428 ◽  
Author(s):  
Milica Mitic ◽  
Mile Stojcev
Keyword(s):  
Interconnection Networks ◽  
Electronics Industry ◽  
Design Reuse ◽  
Design Teams ◽  
Single Chip ◽  
Data Transfers ◽  
System On A Chip ◽  
Design Interfaces ◽  
On Chip ◽  
Levels Of Integration

The electronics industry has entered the era of multi-million-gate chips, and there Xs no turning back. This technology promises new levels of integration on a single chip, called the System-on-a-Chip (SoC) design, but also presents significant challenges to the chip designer. Processing cores on a single chip, may number well into the high tens within the next decade, given the current rate of advancements, [1]. Interconnection networks in such an environment are, therefore, becoming more and more important [2]. Currently on-chip interconnection networks are mostly implemented using buses. For SoC applications, design reuse becomes easier if standard internal connection buses are used for interconnecting components of the design. Design teams developing modules intended for future reuse can design interfaces for the standard bus around their particular modules. This allows future designers to slot the reuse module into their new design simply, which is also based around the same standard bus [3]. In this paper we give an overview of the more popular on-chip bus-based interconnection networks such as AMBA, Avalon CoreConnect, STBus, Wishbone, etc. The main characteristics of the considered buses in respect to topology, arbitration method, bus-width, and types of data transfers are discussed.

scholarly journals Comparison between Vernier-cascade and MZI as transducer for biosensing with on-chip spectral filter

Nanophotonics ◽  
2017 ◽  
Vol 6 (4) ◽  
pp. 703-712 ◽  
Author(s):  
Daan Martens ◽  
Peter Bienstman
Keyword(s):  
Refractive Index ◽  
Power Efficiency ◽  
Point Of Care ◽  
Wavelength Shift ◽  
Spectral Filter ◽  
Higher Power ◽  
Measuring Setup ◽  
Photonic Sensors ◽  
On Chip ◽  
Design Freedom

AbstractThe Mach-Zehnder interferometer (MZI) and the Vernier-cascade are highly responsive photonic sensors with large design freedom. They are therefore very suitable for interrogation through a broadband source and an on-chip spectral filter, a sensing scheme that is well equipped for point-of-care applications. In this work, the MZI is shown to outperform the Vernier-cascade through a better minimum detectable wavelength shift as well as a higher power efficiency, indicating its superiority in this sensing scheme. Fabricated MZIs yield bulk detection limits down to 8.8×10−7 refractive index units (RIU) in a point-of-care compatible measuring setup, indicating the potential of the proposed sensing scheme.

scholarly journals ENERGY AND POWER EFFICIENT SYSTEM ON CHIP WITH NANOSHEET FET

2019 ◽  
Vol 01 (01) ◽  
pp. 51-59 ◽  
Author(s):  
Mohan Kumar N.
Keyword(s):  
Power Dissipation ◽  
Cost Efficiency ◽  
Power Efficiency ◽  
System On Chip ◽  
Noise Tolerance ◽  
Single Chip ◽  
Efficient System ◽  
Power Efficient ◽  
On Chip ◽  
The Cost

As the level of integration of IC increases, System on Chip (SoC) design has evolved. This technology comprises of several intellectual property blocks on a single chip. With downsizing of transistors, the traditional elements used impose several challenges such as power dissipation, leakage and so on. These factors risk the cost efficiency of microsystems and risk the semiconductor industry’s capability to prolong Moore’s law in the nanometer range. This is overcome by the introduction of carbon materials such as nanosheet FET. They are advantageous over the traditional elements in terms of area and power efficiency. We design an energy and power efficient SoC with nanosheet FET that provides noise tolerance and memory optimization.

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