A 2Kx8-bit static MOS RAM with a new memory cell structure

AbstractPhase-change memory is promising because it has a simple structure and has scalability that originates from its unique operating mechanism. However, the programming current should be reduced in accordance with the scaling of cell size [1,2]. We previously reported PCM (Phase Change Memory) cells that operate under 1.5-V/100-μA writing pulses [3, 4]. This PCM had a cell structure composed of 180-nm-W (tungsten) bottom contact to an O-GST (Oxygen-doped GeSbTe) film. Its low-power characteristic is suitable for 0.13-μm generation embedded applications. In the present study, we introduced a new W/O-GST/TaO/W cell structure and found further decrease of programming current the improved stability in the fabrication process. We analyzed the mechanism by which oxygen in GST and the additional TaO layer reduce the power consumption during SET/RESET operations.

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3D domain wall memory-cell structure, array architecture and operation algorithm with anti-disturbance

Microelectronics Journal ◽

10.1016/j.mejo.2017.05.009 ◽

2017 ◽

Vol 66 ◽

pp. 1-8

Author(s):

Yarong Fu ◽

Kai Yang ◽

B.A. Chen ◽

Yinyin Lin

Keyword(s):

Domain Wall ◽

Cell Structure ◽

Memory Cell ◽

Array Architecture ◽

Operation Algorithm ◽

Domain Wall Memory ◽

Structure Array

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Retentivity Studies on Lead Zirconate Titanate Thin Film Capacitors

MRS Proceedings ◽

10.1557/proc-433-273 ◽

1996 ◽

Vol 433 ◽

Cited By ~ 3

Author(s):

In K. Yoo ◽

Chang J. Kim ◽

Seshu B. Desu

Keyword(s):

Lead Zirconate Titanate ◽

Thermal Cycle ◽

Cell Structure ◽

Memory Cell ◽

Lead Zirconate ◽

Theoretical Interpretation ◽

Temperature Cycle ◽

Memory Retention ◽

Zirconate Titanate ◽

Cycle Dependent

AbstractRetention characteristics of various ferroelectric memory cell structures, based on lead zirconate titanate (PZT) capacitors, were investigated under different test conditions. Test of retentivity without any pre-treatment, revealed very high rates of polarization loss with time for partially polarized PZT capacitors. However, when different structures were subjected to a thermal cycle before retentivity study, they indicated significant polarization loss or polarization reversal in FRAM and MFMIS(metal-ferroelectric-metal-insulatorsemiconductor) structures. This thermal cycle dependent retentivity problem was attribute to pyroelectric charges that are developed during the temperature cycle.For each memory cell structure, the underlying mechanisms for the rapid polarization. loss were discussed. Furthermore, guidelines for improving the memory retention were proposed based on the theoretical interpretation of the phenomena.

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Numerical simulation of effective light transmission through a photonic memory cell

Journal of Physics Conference Series ◽

10.1088/1742-6596/2086/1/012090 ◽

2021 ◽

Vol 2086 (1) ◽

pp. 012090

Author(s):

M E Makarov ◽

A A Sapegin ◽

R T Minnullin

Keyword(s):

Numerical Simulation ◽

Light Propagation ◽

Light Transmission ◽

Cell Structure ◽

Memory Cell ◽

Long Distance ◽

Te Mode ◽

Distance Communication ◽

Communication Lines ◽

Change Material

Abstract This paper is devoted to numerical simulation of a non-volatile photonic memory cell based on phase-change material Ge2Sb2Te5. The parameters of light propagation are presented for both crystalline and amorphous Ge2Sb2Te5 phases. The cell structure is optimized for a single TE-mode regime that is suitable for short- and long-distance communication lines.

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Dielectric Engineering to Suppress Cell-to-Cell Programming Voltage Interference in 3D NAND Flash Memory

Micromachines ◽

10.3390/mi12111297 ◽

2021 ◽

Vol 12 (11) ◽

pp. 1297

Author(s):

Woo-Jin Jung ◽

Jun-Young Park

Keyword(s):

Packing Density ◽

Flash Memory ◽

Cell Structure ◽

Memory Cell ◽

Parasitic Capacitance ◽

Nand Flash ◽

Nand Flash Memory ◽

Novel Approach ◽

Flash Memory Cell ◽

Limited Height

In contrast to conventional 2-dimensional (2D) NAND flash memory, in 3D NAND flash memory, cell-to-cell interference stemming from parasitic capacitance between the word-lines (WLs) is difficult to control because the number of WLs, achieved for better packing density, have been dramatically increased under limited height of NAND string. In this context, finding a novel approach based on dielectric engineering seems timely and applicable. This paper covers the voltage interference characteristics in 3D NAND with respect to dielectrics, then proposes an alternative cell structure to suppress such interference.

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