A Wide-Lock-In-Range and Low-Jitter 12-14.5 GHz SSPLL Using a Low-Power Frequency-Disturbance-Detecting and Correcting Loop

Author(s):  
Younghyun Lim ◽  
Juyeop Kim ◽  
Yongwoo Jo ◽  
Jooeun Bang ◽  
Jaehyouk Choi
Keyword(s):  
2020 ◽  
Vol 2 ◽  
pp. 98-102
Author(s):  
Wing-Kong Ng ◽  
Wing-Shan Tam ◽  
Chi-Wah Kok

Author(s):  
Norio Okada ◽  
Shiho Zaizen ◽  
Atsushi Sugitatsu ◽  
Tatsuo Hatta ◽  
Takeshi Fujita ◽  
...  

2017 ◽  
Vol 46 (3) ◽  
pp. 401-414 ◽  
Author(s):  
Motahhareh Estebsari ◽  
Mohammad Gholami ◽  
Mohammad Javad Ghahramanpour

2021 ◽  
Vol 2 (2) ◽  

Techniques for reducing power consumption in digital circuits that underly automatic control of modern engineering systems are of paramount importance due to the simultaneously growing demands for portable multimedia devices and energy conservation. Digital filters, being ubiquitous in such devices, are thus a prime candidate for low power design. We review an algorithmic approach to low power frequency-selective digital filtering, an essential ingredient for energy efficient technological innovation in many domains.


2021 ◽  
Vol 2 (2) ◽  

Techniques for reducing power consumption in digital circuits that underly automatic control of modern engineering systems are of paramount importance due to the simultaneously growing demands for portable multimedia devices and energy conservation. Digital filters, being ubiquitous in such devices, are thus a prime candidate for low power design. We review an algorithmic approach to low power frequency-selective digital filtering, an essential ingredient for energy efficient technological innovation in many domains.


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