A wide range delay locked loop for low power and low jitter applications

2017 ◽  
Vol 46 (3) ◽  
pp. 401-414 ◽  
Author(s):  
Motahhareh Estebsari ◽  
Mohammad Gholami ◽  
Mohammad Javad Ghahramanpour
Keyword(s):  
Low Power ◽  
Delay Locked Loop ◽  
Wide Range ◽  
Low Jitter

An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance

2000 ◽  
Vol 35 (3) ◽  
pp. 377-384 ◽  
Author(s):  
Yongsam Moon ◽  
Jongsang Choi ◽  
Kyeongho Lee ◽  
Deog-Kyoon Jeong ◽  
Min-Kyu Kim
Keyword(s):  
Delay Line ◽  
Delay Locked Loop ◽  
Wide Range ◽  
Low Jitter

A 0.6 V Low-Power Wide-Range Delay-Locked Loop in 0.18 $\mu$m CMOS

2009 ◽  
Vol 19 (10) ◽  
pp. 662-664 ◽  
Author(s):  
Chung-Ting Lu ◽  
Hsieh-Hung Hsieh ◽  
Liang-Hung Lu
Keyword(s):  
Low Power ◽  
Delay Locked Loop ◽  
Wide Range

A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic Half-Delay-Line Architecture

2015 ◽  
Vol 50 (11) ◽  
pp. 2635-2644 ◽  
Author(s):  
Jinn-Shyan Wang ◽  
Chun-Yuan Cheng ◽  
Pei-Yuan Chou ◽  
Tzu-Yi Yang
Keyword(s):  
Low Power ◽  
Delay Line ◽  
Delay Locked Loop ◽  
Wide Range

Design of Low Power Low Jitter Delay Locked Loop in 45 nm CMOS

2021 ◽  
pp. 147-162
Author(s):  
P. Latha ◽  
R. Sivakumar ◽  
Y. V. Ramana Rao ◽  
Thamer Al-Rousan
Keyword(s):  
Low Power ◽  
Delay Locked Loop ◽  
Jitter Delay ◽  
Low Jitter

scholarly journals Low Power Cusped Field Thruster Developed for the Space-Borne Gravitational Wave Detection Mission in China

2021 ◽  
Vol 11 (14) ◽  
pp. 6549
Author(s):  
Hui Liu ◽  
Ming Zeng ◽  
Xiang Niu ◽  
Hongyan Huang ◽  
Daren Yu
Keyword(s):  
Low Power ◽  
Gravitational Wave ◽  
Attitude Control ◽  
High Efficiency ◽  
Experimental Investigations ◽  
Attitude Control System ◽  
Gravitational Wave Detection ◽  
Wave Detection ◽  
Wide Range ◽  
Institute Of Technology

The microthruster is the crucial device of the drag-free attitude control system, essential for the space-borne gravitational wave detection mission. The cusped field thruster (also called the High Efficiency Multistage Plasma Thruster) becomes one of the candidate thrusters for the mission due to its low complexity and potential long life over a wide range of thrust. However, the prescribed minimum of thrust and thrust noise are considerable obstacles to downscaling works on cusped field thrusters. This article reviews the development of the low power cusped field thruster at the Harbin Institute of Technology since 2012, including the design of prototypes, experimental investigations and simulation studies. Progress has been made on the downscaling of cusped field thrusters, and a new concept of microwave discharge cusped field thruster has been introduced.

scholarly journals Design of a high-stability heterogeneous clock system for small satellites in LEO

GPS Solutions ◽  
2021 ◽  
Vol 25 (3) ◽  
Author(s):  
Damon Van Buren ◽  
Penina Axelrad ◽  
Scott Palo
Keyword(s):  
Low Power ◽  
High Stability ◽  
Time Frame ◽  
System Stability ◽  
Small Satellite ◽  
Crystal Oscillator ◽  
Small Satellites ◽  
Clock System ◽  
Wide Range

AbstractWe describe our investigation into the performance of low-power heterogeneous timing systems for small satellites, using real GPS observables from the GRACE Follow-On mission. Small satellites have become capable platforms for a wide range of commercial, scientific and defense missions, but they are still unable to meet the needs of missions that require precise timing, on the order of a few nanoseconds. Improved low-power onboard clocks would make small satellites a viable option for even more missions, enabling radio aperture interferometry, improved radio occultation measurements, high altitude GPS navigation, and GPS augmentation missions, among others. One approach for providing improved small satellite timekeeping is to combine a heterogeneous group of oscillators, each of which provides the best stability over a different time frame. A hardware architecture that uses a single-crystal oscillator, one or more Chip Scale Atomic Clocks (CSACs) and the reference time from a GPS receiver is presented. The clocks each contribute stability over a subset of timeframes, resulting in excellent overall system stability for timeframes ranging from less than a second to several days. A Kalman filter is used to estimate the long-term errors of the CSACs based on the CSAC-GPS time difference, and the improved CSAC time is used to discipline the crystal oscillator, which provides the high-stability reference clock for the small satellite. Simulations using GRACE-FO observations show time error standard deviations for the system range from 2.3 ns down to 1.3 ns for the clock system, depending on how many CSACs are used. The results provide insight into the timing performance which could be achieved on small LEO spacecraft by a low power timing system.

scholarly journals A Fast Lock All-Digital MDLL Using a Cyclic Vernier TDC for Burst-Mode Links

Electronics ◽  
2021 ◽  
Vol 10 (2) ◽  
pp. 177
Author(s):  
Dongjun Park ◽  
Sungwook Choi ◽  
Jongsun Kim
Keyword(s):  
Sampling Technique ◽  
Cmos Process ◽  
Detection Range ◽  
Delay Locked Loop ◽  
Delta Sigma Modulator ◽  
Correlated Double Sampling ◽  
Delta Sigma ◽  
Fast Power ◽  
Low Jitter ◽  
Reference Clock

An all-digital multiplying delay-locked loop (MDLL)-based clock multiplier featuring a time-to-digital converter (TDC) to achieve fast power-on capability is presented. The proposed MDLL adopts a new offset-free cyclic Vernier TDC to achieve a fast lock time of 15 reference clock cycles while maintaining a wide detection range and high resolution. The proposed offset-free TDC also uses a correlated double sampling technique to remove mismatch and offset issues, resulting in low jitter characteristics. After the MDLL is quickly locked, the TDC is turned off, and it goes into delta-sigma modulator (DSM)-based sequential tracking mode to reduce power consumption and improve jitter performance. Implemented in a 65-nm 1.0-V CMOS process, the proposed MDLL occupies an active area of 0.043 mm2 and generates a 2.4-GHz output clock from a 75-MHz reference clock (multiplication factor N = 32). It achieves an effective peak-to-peak jitter of 9.4 ps and consumes 3.3 mW at 2.4 GHz.

A wide range low power CMOS radio frequency ring oscillator

2009 ◽  
Author(s):  
Huimin Liu ◽  
Xiaoxing Zhang ◽  
Yujie Dai ◽  
Yingjie Lu ◽  
Baolin Wei
Keyword(s):  
Low Power ◽  
Radio Frequency ◽  
Ring Oscillator ◽  
Wide Range ◽  
Low Power Cmos

scholarly journals Wide-Range Dynamic Power Management in Low-Voltage Low-Power Subthreshold SCL

2012 ◽  
Vol 59 (12) ◽  
pp. 903-907 ◽  
Author(s):  
Armin Tajalli ◽  
Yusuf Leblebici
Keyword(s):  
Low Power ◽  
Power Management ◽  
Low Voltage ◽  
Dynamic Power Management ◽  
Dynamic Power ◽  
Wide Range
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