Highly Uniform Eight-Channel SOA-Gate Array With High Saturation Output Power and Low Noise Figure

2007 ◽  
Vol 19 (16) ◽  
pp. 1275-1277 ◽  
Author(s):  
S. Tanaka ◽  
S. Tomabechi ◽  
A. Uetake ◽  
M. Ekawa ◽  
K. Morito
Keyword(s):  
Output Power ◽  
Noise Figure ◽  
Low Noise ◽  
High Saturation ◽  
Gate Array ◽  
Highly Uniform

A Highly-Integrated, Switchless and Baluns-Embedded Transceiver with a Differential Structure for C-Band Radar Application

2019 ◽  
Vol 29 (10) ◽  
pp. 2050160
Author(s):  
Guoxiao Cheng ◽  
Zhiqun Li ◽  
Zhennan Li ◽  
Zengqi Wang ◽  
Meng Zhang
Keyword(s):  
Output Power ◽  
Noise Figure ◽  
Low Noise ◽  
Cmos Process ◽  
Image Rejection ◽  
Rf Switch ◽  
Differential Structure ◽  
Noise Amplifier ◽  
Image Rejection Ratio ◽  
Better Than

This paper presents a highly-integrated transceiver with a differential structure for C-band (5–6[Formula: see text]GHz) radar application using a switchless and baluns-embedded configuration. To reduce the noise figure (NF) in receiver (Rx) mode and enhance the output power in transmitter (Tx) mode, the balun at RF port is embedded into the low-noise amplifier (LNA) and the power amplifier (PA), respectively. Besides, the RF switch is removed by designing the matching networks that both LNA and PA can share. The same topology is also adopted at the IF port. To achieve a high image rejection ratio (IRR), a Hartley architecture using polyphase filters (PPFs) is adopted. The proposed transceiver has been implemented in 1P6M 0.18-[Formula: see text]m CMOS process. The receiver achieves 6.9-dB NF, [Formula: see text]7.5-dBm IIP3 and 26.3-dB gain with three-step digital gain controllability. Also the measured IRR is better than 41[Formula: see text]dBc. The transmitter achieves 9.6-dBm output power and 19.2-dB gain. The chip consumes 106[Formula: see text]mA in the Rx mode and 141[Formula: see text]mA in the Tx mode from the 3.3-V power supply.

scholarly journals GaN low-noise X-band MMIC amplifier.

2021 ◽  
Vol 2021 (2) ◽  
Author(s):  
E. Kudabay ◽  
◽  
A. Salikh ◽  
V.A. Moseichuk ◽  
A. Krivtsun ◽  
...  
Keyword(s):  
Output Power ◽  
Integrated Circuit ◽  
Noise Figure ◽  
Supply Voltage ◽  
High Electron Mobility Transistor ◽  
Low Noise ◽  
Common Source ◽  
High Electron ◽  
Monolithic Integrated Circuit ◽  
X Band

The purpose of this paper is to design a microwave monolithic integrated circuit (MMIC) for low noise amplifier (LNA) X-band (7-12 GHz) based on technology of gallium nitride (GaN) high electron mobility transistor (HEMT) with a T-gate, which has 100 nm width, on a silicon (Si) semi-insulating substrate of the OMMIC company. The amplifier is based on common-source transistors with series feedback, which was formed by high-impedance transmission line, and with parallel feedback to match noise figure and power gain. The key characteristics of an LNA are noise figure and gain. However, in this paper, it was decided to design the LNA, which should have a good margin in terms of input and output power. As a result, GaN technology was chosen, which has a higher noise figure compared to other technologies, but eliminates the need for an input power limiter, which in turn significantly increases the overall noise figure. As a result LNA MMIC was developed with the following characteristics: noise figure less than 1.6 dB, small-signal gain more than 20 dB, return loss better than -13 dB and output power more than 19 dBm with 1 dB compression in the range from 7 to 12 GHz in dimensions 2x1.5 mm², which has a supply voltage of 8 V and a current consumption of less than 70 mA. However, it should be said that LNA was only modeled in the AWR DE.

Materials and Device Characteristics of InAlAs/InGaAs HEMTs

1992 ◽  
Vol 281 ◽  
Author(s):  
Pin Ho ◽  
M. Y. Kao ◽  
P. C. Chao ◽  
K. H. G. Duh ◽  
P. M. Smith ◽  
...  
Keyword(s):  
Power Density ◽  
Output Power ◽  
Electron Mobility ◽  
Noise Figure ◽  
Low Noise ◽  
Maximum Output ◽  
High Electron ◽  
60 Ghz ◽  
Power Gain ◽  
Power Added Efficiency

ABSTRACTHigh electron mobility transistors (HEMTs) based on the InAlAs/InGaAs heterostructure have been grown on InP by molecular beam epitaxy. At room temperature, typical sheet charge densities of 2.1–3.0×1012 cm−2 and Hall electron mobilities over 10000 cm2 /V-s are obtained. An electron mobility as high as 13000 cm2 /V-s is achieved with a pseudomorphic Iny Ga1−y As channel and a y value of 0.70.HEMTs with a T- or Γ-shaped gate and with gate lengths ranging from 0.1–0.25 urn have been fabricated. A record low noise figure of 0.7 dB with an associated gain of 8.6 dB at 62 GHz has been achieved with 0.1 μm Γ-gate devices, while T-gate devices exhibit a minimum noise figure of 1.2 dB with 7.2 dB associated gain at 94 GHz. Separately, a record fmax value of 455 GHz was determined by extrapolating at -6 dB/octave from the measured gain of 13.6 dB at 95 GHz.Power HEMTs using a double heterojunction structure exhibit a record peak power-added efficiency (P.A.E.) of 49% with 8.6 dB power gain and 0.30 W/mm power density measured at 60 GHz. When biased and tuned for maximum output power, our best 60 GHz output power density to date is 0.52 W/mm with 33% P.A.E. and 5.9 dB power gain using a single heterojunction HEMT scheme with pseudomorphic channel. A similar device also yields peak P.A.E. of 26% with 0.20 W/mm power density and 4.9 dB gain at 94 GHz. These results represent the highest P.A.E.S and power gains ever reported for any transistor at these frequencies.

Design Exploration of mm-Wave Integrated Transceivers for Short-Range Mobile Communications Towards 5G

2016 ◽  
Vol 26 (04) ◽  
pp. 1750069 ◽  
Author(s):  
Sergio Saponara ◽  
Filippo Giannetti ◽  
Bruno Neri
Keyword(s):  
Power Consumption ◽  
Output Power ◽  
Mobile Communications ◽  
Short Range ◽  
Noise Figure ◽  
Wave Spectrum ◽  
Average Power ◽  
Low Noise ◽  
System Level ◽  
Design Exploration

This paper presents a design exploration, at both system and circuit levels, of integrated transceivers for the upcoming fifth generation (5G) of wireless communications. First, a system level model for 5G communications is carried out to derive transceiver design specifications. Being 5G still in pre-standardization phase, a few currently used standards (ECMA-387, IEEE 802.15.3c, and LTE-A) are taken into account as the reference for the signal format. Following a top-down flow, this work presents the design in 65[Formula: see text]nm CMOS SOI and bulk technologies of the key blocks of a fully integrated transceiver: low noise amplifier (LNA), power amplifier (PA) and on-chip antenna. Different circuit topologies are presented and compared allowing for different trade-offs between gain, power consumption, noise figure, output power, linearity, integration cost and link performance. The best configuration of antenna and LNA co-design results in a peak gain higher than 27[Formula: see text]dB, a noise figure below 5[Formula: see text]dB and a power consumption of 35[Formula: see text]mW. A linear PA design is presented to face the high Peak to Average Power Ratio (PAPR) of multi-carrier transmissions envisaged for 5G, featuring a 1[Formula: see text]dB compression point output power (OP1dB) of 8.2[Formula: see text]dBm. The delivered output power in the linear region can be increased up to 13.2[Formula: see text]dBm by combining four basic PA blocks through a Wilkinson power combiner/divider circuit. The proposed circuits are shown to enable future 5G connections, operating in a mm-wave spectrum range (spanning 9[Formula: see text]GHz, from 57[Formula: see text]GHz to 66[Formula: see text]GHz), with a data-rate of several Gb/s in a short-range scenario, spanning from few centimeters to tens of meters.

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