CMOS technologies are suffering from increased variability due to process, supply voltage and temperature (PVT) variations as we enter the tens-of-nanometer regime. Analog and mixed-signal circuits have failed to effectively exploit the high-speed and low-noise properties that deep scaled CMOS technologies provide due to marginality issues. Large variations in leakage current and threshold voltage also make highly integrated digital designs challenging. In addition, device aging introduces a temporal dimension to variations in circuit performance. Consequently, there is an increasing need for a new design methodology that can provide high yield and reliability under severe parametric variations. Although several post-silicon calibration and repair strategies have been proposed to address the PVT variations, no coherent design strategy for a SoC has been developed so far. We espouse a self-healing technique based on real-time sensing and built-in feedback due to its inherent advantage of dynamic adaptation to temporal variations. This tutorial paper outlines our vision of improving marginalities in deep scaled CMOS technologies using a generic and systematic self-healing design including a system-level auto-correction algorithm. It also illustrates this methodology with design examples.
