Dynamic Specification Testing and Diagnosis of High-Precision Sigma-Delta ADCs

In this paper, a design of a digital decimation filter which has a output of 24 bits for high-precision 4-ordes Σ-Δ ADC is proposed. The digital decimation filter includes a CIC filter, a compensation filter and a half band filter. The over-sampling rate of the digital decimation filter is 256, the cutoff frequency is 1kHz, the coefficient of the pass-band ripple is -0.25dB, the stop-band attenuation is -162dB, simulation results using Matlab and modelsim are correct, the result of the FPGA verification shows that the design meet the requirement of the high-precision 4-ordes Σ-Δ ADC.

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A FPGA-based 7-order 1-bit sigma-delta modulator for high-precision signal generation

2009 9th International Conference on Electronic Measurement & Instruments ◽

10.1109/icemi.2009.5274097 ◽

2009 ◽

Cited By ~ 3

Author(s):

Song Hongzhi ◽

Wu Jie ◽

Ma Yichao ◽

Kong Yang ◽

Zhang Jie

Keyword(s):

High Precision ◽

Signal Generation ◽

Sigma Delta Modulator ◽

Sigma Delta

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A High Precision PCM Codec Using Sigma-Delta Modulation

10.1109/esscirc.1988.5468467 ◽

1988 ◽

Author(s):

V. Friedman ◽

D-P. Chen ◽

E. M. Fields ◽

J. W. Scott ◽

T. R. Viswanathan

Keyword(s):

High Precision ◽

Sigma Delta Modulation ◽

Sigma Delta ◽

Delta Modulation

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A Noise-Optimal Integrator for High-Precision SC Sigma Delta Modulators

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.644-650.3322 ◽

2014 ◽

Vol 644-650 ◽

pp. 3322-3328

Author(s):

Xiao Lei Wang ◽

Yong Wei Zhang

Keyword(s):

High Precision ◽

Supply Voltage ◽

Cmos Technology ◽

Bottom Plate ◽

Noise Power ◽

Power Supply Voltage ◽

Sigma Delta Modulator ◽

Sigma Delta ◽

Sigma Delta Modulators ◽

The Right

Based on N-well Chartered 0.35-um CMOS technology, we designed an integrator for a low-power and high-precision sigma-delta modulator, which has a structure of third-order CIFF, one bit quantization. Amplifier designed in this paper use the PMOS folded cascade differential structure. All switches of the switch capacitance integrator are CMOS switch. The structure-improved integrator can be used to preliminarily filter the noise power of the input signal, and reduce the noise into the modulator, combined with bottom plate sampling technology and the right timing sequence. Input sinusoidal signal has frequency of 65.625Hz and amplitude of 0.6V. It’s simulated in cadence spectre with sampling frequency of 76.8kHz and power supply voltage of 3.3V. FFT analysis of the integrator output shows that the noise floor is-94.3dB, which meets the performance requirements of the system.

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