Design of a Digital Decimation Filter for High-Precision 4-Order Sigma-Delta ADC

2012 ◽  
Vol 503 ◽  
pp. 415-419 ◽  
Author(s):  
Wei Ping Chen ◽  
Qiang Fu ◽  
Xiao Wei Liu ◽  
Yan Xiao ◽  
Bin Zhang ◽  
...  
Keyword(s):  
High Precision ◽  
Sampling Rate ◽  
Stop Band ◽  
Cutoff Frequency ◽  
Pass Band ◽  
Sigma Delta ◽  
Band Filter ◽  
Cic Filter ◽  
Decimation Filter ◽  
Sigma Delta Adc

In this paper, a design of a digital decimation filter which has a output of 24 bits for high-precision 4-ordes Σ-Δ ADC is proposed. The digital decimation filter includes a CIC filter, a compensation filter and a half band filter. The over-sampling rate of the digital decimation filter is 256, the cutoff frequency is 1kHz, the coefficient of the pass-band ripple is -0.25dB, the stop-band attenuation is -162dB, simulation results using Matlab and modelsim are correct, the result of the FPGA verification shows that the design meet the requirement of the high-precision 4-ordes Σ-Δ ADC.

scholarly journals FPGA Based Performance Analysis of Multistage CIC Decimation Filter Design with former CIC Filter for WiMAX Applications

2019 ◽  
Vol 8 (6) ◽  
pp. 5084-5089
Keyword(s):  
Frequency Response ◽  
Filter Design ◽  
Stop Band ◽  
Pass Band ◽  
Two Stage ◽  
Simulink Model ◽  
Cic Filter ◽  
Decimation Filter ◽  
Two Stages ◽  
Kaiser Window

The motto of this paper is to design and realize decimation filter using CIC filter. The main drawback of this filter is there is large droop in pass band and very less attenuation in stop band. So, to improve the frequency response of CIC filter we go for two stage realization of CIC filter. At the initial stage we use CIC filter and in the last stage we use Kaiser Window and improve the characteristics of filter design. When we design a filter using multistage methodology the order of the filter as well as power also decreases. Tools used are MATLAB Simulink Model and Xilinx system generator and realization is done on Virtex V-XC5VLX110T-3ff136. In this paper the proposed two stage realization is compared with respect to two stages Kaiser window realization in the terms of number of LUT’s required, slices as well as power dissipation and improvements in frequency response with respect to conventional CIC filter are compared

Design and Simulation of Switched Capacitor Filter for Speed Change Parameter Converter

2013 ◽  
Vol 562-565 ◽  
pp. 1132-1136
Author(s):  
Xiao Wei Liu ◽  
Jian Yang ◽  
Song Chen ◽  
Liang Liu ◽  
Rui Zhang ◽  
...  
Keyword(s):  
Stop Band ◽  
Cutoff Frequency ◽  
Rapid Change ◽  
Pass Band ◽  
Cmos Process ◽  
Switched Capacitor ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Low Pass ◽  
The Time Domain

In this paper, we design a high-order switched capacitor filter for rapid change parameter converter. This design uses a structure which consists of three biquads filter sub-units. The design is a 6th-order SC elliptic low-pass filter, and the sample frequency is 250 kHz. By the MATLAB Simulink simulation, the system can meet the design requirements in the time domain. In this paper, the 6th-order switched capacitor elliptic low-pass filter was implemented under 0.5 um CMOS process and simulated in Cadence. The final simulation results show that the pass-band cutoff frequency is 10 kHz, and the maximum pass-band ripple is about 0.106 dB. The stop-band cutoff frequency is 20 kHz, and the minimum stop-band attenuation is 74.78 dB.

scholarly journals A Sigma-Delta ADC for Signal Conditioning IC of Automotive Piezo-Resistive Pressure Sensors with over 80 dB SNR

Sensors ◽  
2018 ◽  
Vol 18 (12) ◽  
pp. 4199 ◽  
Author(s):  
Behnam Samadpoor Rikan ◽  
Sang-Yun Kim ◽  
Nabeel Ahmad ◽  
Hamed Abbasizadeh ◽  
Muhammad Riaz Ur Rehman ◽  
...  
Keyword(s):  
Input Signal ◽  
Flicker Noise ◽  
Signal To Noise Ratio ◽  
Pressure Sensors ◽  
High Gain ◽  
Cmos Process ◽  
Signal Conditioning ◽  
Sigma Delta ◽  
Cic Filter ◽  
Decimation Filter

This paper presents a second-order discrete-time Sigma-Delta (SD) Analog-to-Digital Converter (ADC) with over 80 dB Signal to Noise Ratio (SNR), which is applied in a signal conditioning IC for automotive piezo-resistive pressure sensors. To reduce the flicker noise of the structure, choppers are used in every stage of the high gain amplifiers. Besides, to reduce the required area and power, only the CIC filter structure is adopted as a decimation filter. This filter has a configurable structure that can be applied to different data rates and input signal bandwidths. The proposed ADC was fabricated and measured in a 0.18-µm CMOS process. Due to the application of only a CIC filter, the total active area of the SD-ADC and reference generator is 0.49 mm2 where the area of the decimation filter is only 0.075 mm2. For the input signal bandwidth of 1.22 kHz, it achieved over 80 dB SNR in a 2.5 MHz sampling frequency while consuming 646 µW power.

Design of Third-Order Single-Loop Full Feed-Forward Sigma Delta Modulator

2014 ◽  
Vol 609-610 ◽  
pp. 1176-1180
Author(s):  
Liang Liu ◽  
Song Chen ◽  
Chong He ◽  
Liang Yin ◽  
Xiao Wei Liu
Keyword(s):  
Model Building ◽  
Inertial Sensors ◽  
Sampling Rate ◽  
Third Order ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Feed Forward ◽  
Single Loop ◽  
Local Feedback ◽  
Sigma Delta Adc

Sigma Delta modulator is widely used in ADC for kinds of micro inertial sensors, Sigma Delta ADC can be easily integrated with digital circuits. It possesses some performances of good linearity and high accuracy, while it has no such strict requirements for the match of device dimensions. In this paper, the design of third-order Sigma Delta modulator with a structure of single-loop full feed-forward is accomplished, meanwhile it uses local feedback for zero optimization to improve the shaping capacity of the modulator noise within the signal bandwidth. The OSR (over-sampling rate) of the modulator is 128 and the signal bandwidth is 10 kHz. By the system model building and simulation in the Simulink of MATALAB, the SNR is 96.3 dB and the ENOB is 15.71 bits. Then the modulator is implemented into transistor-level circuits with 0.5um process, by the simulation in Spectre of Cadence, the SNR is 88.5 dB and the ENOB is 14.41 bits. 搜

scholarly journals Design and implementation of novel FPGA based time-interleaved variable centre-frequency digital Σ−Δ modulators

ACTA IMEKO ◽  
2015 ◽  
Vol 4 (1) ◽  
pp. 68
Author(s):  
Isil Kalafat Kizilkaya ◽  
Mohammed Al-Janabi ◽  
Izzet Kale
Keyword(s):  
Electromagnetic Interference ◽  
Dynamic Range ◽  
Stop Band ◽  
Pass Band ◽  
Signal To Noise ◽  
Sigma Delta ◽  
Sigma Delta Modulators ◽  
Centre Frequency ◽  
Sinusoidal Input ◽  
Time Interleaved

Multiresolution analog-to-digital converters (MRADC) are usually used in Time Domain ElectroMagnetic Interference (TDEMI) measuring systems for very fast signal sampling with a sufficient dynamic range. The properties of the spectrum measured by the TDEMI system influenced by imperfections in the MRADC are analyzed in this paper. Errors are caused by imperfect matching of the offset and gain and phase of the circuits used in parallel input channels typical for the MRADC. For deep analyses of MRADC behavior, a precise mathematical model has been created using the concept of additive error pulses. Furthermore, a dedicated process of the identification of discrepancy parameters from experimental data is proposed. Identified parameters enter the expressions of the model and enable side to side comparison of experimental and theoretical results.Novel, multi-path, time-interleaved digital sigma-delta modulators that can operate at any arbitrary frequency from DC to Nyquist are designed, analysed and synthesized in this study. Dual- and quadruple-path fourth-order Butterworth, Chebyshev, Inverse Chebyshev and Elliptical based digital sigma-delta modulators, which offer designers the flexibility of specifying the centre-frequency, pass-band/stop-band attenuation as well as the signal bandwidth are presented. These topologies are compared in terms of their signal-to-noise ratios, hardware complexity, stability, tonality and sensitivity to non-idealities. Detailed simulations performed at the behavioural-level in MATLAB are compared with the experimental results of the FPGA implementation of the designed modulators. The signal-to-noise ratios between the simulated and empirical results are shown to be different by not more than 3-5 dBs. Furthermore, this paper presents the mathematical modelling and evaluation of the tones caused by the finite wordlengths of these digital multi-path sigma-delta modulators when excited by sinusoidal input signals.

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