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Author(s):  
S. Lalitha ◽  
K. Maheshkumar ◽  
R. Shobana ◽  
C. Deepika

AbstractObjectivesKapalbhathi Pranayam (Kapal = forehead; bhati = shining) is a breathing exercise that has been practiced to cleanse the frontal brain in traditional practices like yoga. Still, there exists a dearth of literature on the effect of Kapalbhathi pranayama on physiological systems. So this present study was carried out to find the immediate effect of “kapalbhathi Pranayam” practice for the period of 5 min on cardiac autonomic function among the healthy volunteers.Materials and methodsApparently 50 healthy volunteers includes both sex were participated. They were randomly divided into Pranayama (n−25) and control (n−25) group. Pranayama group was practiced kapalbhathi pranayama 5 min (5 cycles) and control group was allowed to do normal breathing (12–16 breath/min). Lead II ECG was recorded for 5 min using simple AD converter before, immediately after practice and 20 min of recovery period.ResultsOne way Analysis of variance (ANOVA) followed by post hoc test was done using R statistical software. There was a significant (p < 0.05) parasympathetic withdrawal (Root Mean Square of the Successive Differences (RMSSD) – p < 0.04 and HF n.u – p < 0.05) was found in the pranayama group immediately after practice and its was changed to parasympathetic domination (RMSSD – p < 0.04 and HF n.u – p < 0.05) after 20 min of recovery period.ConclusionThe present study suggested that though there was parasympathetic withdrawal immediately after practicing kapalbhathi pranayama, 20 min after the recovery period showed a parasympathetic domination in the pranayama group subjects. However, further studies are required to warrant the findings of this study.


Author(s):  
Sanshiro Kimura ◽  
Atsuto Imajo ◽  
Toshiyuki Inoue ◽  
Akira Tsuchiya ◽  
Keiji Kishine

2016 ◽  
Vol 63 (3) ◽  
pp. 234-238 ◽  
Author(s):  
Mauro Santos ◽  
Nuno Horta ◽  
Jorge Guilherme

2015 ◽  
Vol 135 (1) ◽  
pp. 18-25
Author(s):  
Toshiki Sugimoto ◽  
Hiroshi Tanimoto ◽  
Shingo Yoshizawa
Keyword(s):  

2014 ◽  
Vol 1079-1080 ◽  
pp. 1038-1041
Author(s):  
Yan Zhao ◽  
Jiang Hua Wang ◽  
Kun Li

The digital oscilloscope adopts STM32 MCU as the control core, uses the IDT7201 for memory, through the AD converter ADS830 real-time sampling achieve the extraction of the input signal and digital storage, display; Crossover functions are realized by CPLD to provide accurate clock for MCU, FIFO, ADS830, and communicate with MCU through SPI agreement. Software design to achieve control A/D converter start-up and storage of the sample data, calculate the frequency and amplitude, buttons and LCD screen.Using Altium Designer software to design and produce a digital oscilloscope printed circuit board PCB, and complete the whole production and commissioning. The digital oscilloscope can be real-time accurate sampling and show the general low frequency signal, can be used when using battery power, small volume, convenient to carry, it can be easily integrated into the experiment box, to become a part of it, and other function modules to form a whole.


2014 ◽  
Vol 539 ◽  
pp. 65-69
Author(s):  
Xiao Ming Yang

DDFS is widely used in digital signal processing and communications. Orthogonal sine wave oscillator is the main part of DDFS. In this paper, a new CORDIC algorithm implemented based on FPGA is proposed to realize DDFS. Replace the traditional look-up table ROM method to CORDIC algorithm. The algorithm has been realized in the FPGA using the pipeline architecture. The design has the advantages of little hardware resource consumption, high accuracy, and without memory. At the end, give a simulation waveform and spectrum analysis by AD converter, show the result in oscilloscope.


2014 ◽  
Vol 556-562 ◽  
pp. 1652-1655
Author(s):  
Jian Hong Zhu ◽  
Shao Peng Yang ◽  
Mei Feng Gao

In order to ensure the linear array CCD normally and stably working in the spectral measurement, the data acquisition and storage circuit is presented. On the basis of analyzing the ILX511 driving timing, the circuit of data acquisition, processing, and storage based on CCD was designed. The CPLD was used to establish the correct sequence for the CCD clock pulse, AD converter clock, and FIFO writing signal, so the data acquisition, converter, and storage synchronously are achieved. The experiments show that the designed circuit is feasible.


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