An 8Gbps discrete time linear equalizer in 40nm CMOS technology

Author(s):  
Ahmed Ismail ◽  
Sameh Ibrahim ◽  
Mohamed Dessouky
2017 ◽  
Vol 26 (12) ◽  
pp. 1750199 ◽  
Author(s):  
Maedeh Fallahi ◽  
Abumoslem Jannesari

In this paper, a switched resistor slicer is proposed to reduce the power consumption of a decision feedback equalizer (DFE). In the proposed structure, summer circuit that consumes most of the power in a DFE has been eliminated and proper resistors are added as the load of a slicer based on a flip-flop output bit stream. Incorporating the proposed DFE circuit with continuous time linear equalizer (CTLE) at the serial link receiver over a 1[Formula: see text]m NELCO (the NELCO[Formula: see text] N4000-13 series is an enhanced epoxy resin system engineered to provide both outstanding thermal and high signal speed/low signal loss properties) channel can compensate 24[Formula: see text]dB loss at the Nyquist frequency of 2[Formula: see text]GHz. CTLE is adjusted to compensate 6[Formula: see text]dB of channel loss which remains after utilizing a DFE with three taps. The proposed structure has been designed in 0.18[Formula: see text][Formula: see text]m CMOS technology while consuming 13.5[Formula: see text]mW from 1.8[Formula: see text]V supply at 4[Formula: see text]Gb/s with a bit error rate less than 10[Formula: see text]. The proposed equalizer power consumption is reduced by 43% compared to the conventional circuit.


2012 ◽  
Vol 22 (4) ◽  
pp. 451-465 ◽  
Author(s):  
Tadeusz Kaczorek

A new modified state variable diagram method is proposed for determination of positive realizations with reduced numbers of delays and without delays of linear discrete-time systems for a given transfer function. Sufficient conditions for the existence of the positive realizations of given proper transfer function are established. It is shown that there exists a positive realization with reduced numbers of delays if there exists a positive realization without delays but with greater dimension. The proposed methods are demonstrated on a numerical example.


Sensors ◽  
2021 ◽  
Vol 21 (7) ◽  
pp. 2307
Author(s):  
Sofiane Bououden ◽  
Ilyes Boulkaibet ◽  
Mohammed Chadli ◽  
Abdelaziz Abboudi

In this paper, a robust fault-tolerant model predictive control (RFTPC) approach is proposed for discrete-time linear systems subject to sensor and actuator faults, disturbances, and input constraints. In this approach, a virtual observer is first considered to improve the observation accuracy as well as reduce fault effects on the system. Then, a real observer is established based on the proposed virtual observer, since the performance of virtual observers is limited due to the presence of unmeasurable information in the system. Based on the estimated information obtained by the observers, a robust fault-tolerant model predictive control is synthesized and used to control discrete-time systems subject to sensor and actuator faults, disturbances, and input constraints. Additionally, an optimized cost function is employed in the RFTPC design to guarantee robust stability as well as the rejection of bounded disturbances for the discrete-time system with sensor and actuator faults. Furthermore, a linear matrix inequality (LMI) approach is used to propose sufficient stability conditions that ensure and guarantee the robust stability of the whole closed-loop system composed of the states and the estimation error of the system dynamics. As a result, the entire control problem is formulated as an LMI problem, and the gains of both observer and robust fault-tolerant model predictive controller are obtained by solving the linear matrix inequalities (LMIs). Finally, the efficiency of the proposed RFTPC controller is tested by simulating a numerical example where the simulation results demonstrate the applicability of the proposed method in dealing with linear systems subject to faults in both actuators and sensors.


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