A VHDL-Based Technique for an Accurate Estimation-of Leakage Power in Digital CMOS Circuits

Author(s):  
A. Nourivand ◽  
Chunyan Wang ◽  
M.O. Ahmad
2003 ◽  
Vol 1 ◽  
pp. 223-228
Author(s):  
C. Schlachta ◽  
M. Glesner

Abstract. One of the possible techniques to reduces the power consumption in digital CMOS circuits is to slow down the charge transport. This slowdown can be achieved by introducing an inductor in the charging path. Additionally, the inductor can act as an energy storage element, conserving the energy that is normally dissipated during discharging. Together with the parasitic capacitances from the circuit a LCresonant circuit is formed.


Sign in / Sign up

Export Citation Format

Share Document