Accurate Estimation of Leakage Power Variability in Sub-micrometer CMOS Circuits

2012 ◽  
Author(s):  
Omid Assare ◽  
Mahmoud Momtazpour ◽  
Maziar Goudarzi
Keyword(s):  
Leakage Power ◽  
Accurate Estimation ◽  
Cmos Circuits

scholarly journals Estimation of Leakage Power and Delay in CMOS Circuits

2020 ◽  
Vol 4 (7) ◽  
pp. 14-19
Author(s):  
Mohasinul Huq N Md ◽  
Mohan Das S ◽  
Bilal N Md
Keyword(s):  
Power Dissipation ◽  
Supply Voltage ◽  
Full Adder ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Leakage Power ◽  
Nand Gate ◽  
High Threshold ◽  
Cmos Circuits ◽  
Low Leakage

This paper presents an estimation of leakage power and delay for 1-bit Full Adder (FA)designed which is based on Leakage Control Transistor (LCT) NAND gates as basic building block. The main objective is to design low leakage full adder circuit with the help of low and high threshold transistors. The simulations for the designed circuits performed in cadence virtuoso tool with 45 nm CMOS technology at a supply voltage of 0.9 Volts. Further, analysis of effect of parametric variation on leakage current and propagation delay in CMOS circuits is performed. The saving in leakage power dissipation for LCT NAND_HVT gate is up to 72.33% and 45.64% when compared to basic NAND and LCT NAND gate. Similarly for 1-bit full adder the saving is up to 90.9% and 40.08% when compared to basic NAND FA and LCT NAND.

scholarly journals Leakage Current Reduction in CMOS Circuits Using Stacking Technique

2020 ◽  
pp. 175-178
Author(s):  
N. Geetha Rani ◽  
G. Ragapriya ◽  
Harshitha V ◽  
G. Swetha ◽  
B. Sri Jyothi
Keyword(s):  
Leakage Current ◽  
Leakage Power ◽  
Cmos Circuits ◽  
Rapid Progress ◽  
Semiconductor Technology ◽  
Single Chip ◽  
Leakage Currents ◽  
Current Reduction

This paper deals with The rapid progress in semiconductor technology have led the feature sizes of transistor to be shrunk there by evolution of Deep Sub-Micron (DSM) technology. There by the extremely complex functionality is enabled to be integrated on a single chip. So, transistor size is reduced to few nanometers. By reducing the size drastically some problems are occurred. In that leakage power is one of the disadvantage. By using this stacking technique we are going to reduce the leakage currents.

scholarly journals Review of Leakage Power Reduction in CMOS Circuits

2014 ◽  
Vol 2 (4) ◽  
pp. 133-136 ◽  
Author(s):  
Khushboo Kumari ◽  
Arun Agarwal ◽  
J Jayvrat ◽  
Kabita Agarwal
Keyword(s):  
Power Reduction ◽  
Leakage Power ◽  
Cmos Circuits

Leakage Power Estimation of Adiabatic Circuits Using SPICE in Nanometer CMOS Processes

2010 ◽  
Vol 108-111 ◽  
pp. 625-630 ◽  
Author(s):  
Yang Bo Wu ◽  
Jian Ping Hu ◽  
Hong Li
Keyword(s):  
Significant Proportion ◽  
Power Estimation ◽  
Low Power Design ◽  
Leakage Power ◽  
Cmos Process ◽  
Cmos Circuits ◽  
Nanometer Cmos ◽  
Adiabatic Logic ◽  
Total Leakage ◽  
Pass Transistor

In deep sub-micro CMOS process, the leakage power is becoming a significant proportion in power dissipation. Hence, estimating the leakage power of CMOS circuits is very important in low-power design. In this paper, an estimation technology for the total leakage power of adiabatic logic circuits by using SPICE is proposed. The basic principle of power estimation for traditional CMOS circuits using SPICE is introduced. According to the energy dissipation characteristic of adiabatic circuits, the estimation technology for leakage power is discussed. Taken as an example, the estimation for total leakage power dissipations of PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) circuits is illustrated using the proposed estimation technology.

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