Statistical power optimization of deep-submicron digital CMOS circuits based on structured perceptron

2014 International Symposium on Integrated Circuits (ISIC) ◽

10.1109/isicir.2014.7029446 ◽

2014 ◽

Author(s):

Amir Zjajo ◽

Nick van der Meijs ◽

Rene van Leuken

Keyword(s):

Statistical Power ◽

Power Optimization ◽

Deep Submicron ◽

Cmos Circuits ◽

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Static power optimization of deep submicron CMOS circuits for dual VT technology

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) ◽

10.1145/288548.289076 ◽

1998 ◽

Author(s):

Qi Wang ◽

Sarma B. K. Vrudhula

Keyword(s):

Power Optimization ◽

Deep Submicron ◽

Cmos Circuits ◽

Static Power ◽

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Static power optimization of deep submicron CMOS circuits for dual V/sub T/ technology

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) ◽

10.1109/iccad.1998.742957 ◽

2002 ◽

Author(s):

Qi Wang ◽

S.B.K. Vrudhula

Keyword(s):

Power Optimization ◽

Deep Submicron ◽

Cmos Circuits ◽

Static Power ◽

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Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits

2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools ◽

10.1109/dsd.2008.90 ◽

2008 ◽

Author(s):

Enrico Macii ◽

Leticia Bolzani ◽

Andrea Calimera ◽

Alberto Macii ◽

Massimo Poncino

Keyword(s):

Power Optimization ◽

Leakage Power ◽

Cmos Circuits ◽

Power Gating ◽

Clock Gating ◽

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Generic linear RC delay modeling for digital CMOS circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.45868 ◽

1990 ◽

Vol 9 (4) ◽

pp. 367-376 ◽

Author(s):

A.-C. Deng ◽

Y.-C. Shiau

Keyword(s):

Cmos Circuits ◽

Digital Cmos ◽

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Power Optimization Opportunities for a Reconfigurable Arithmetic Component in the Deep Submicron Domain

2012 15th Euromicro Conference on Digital System Design ◽

10.1109/dsd.2012.105 ◽

2012 ◽

Author(s):

Dimitris Bekiaris ◽

George Economakos

Keyword(s):

Power Optimization ◽

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Amplification, feedback, and sub-biasing: Applying analog techniques to high-speed, low-power digital CMOS circuits

2017 International Symposium on Signals, Circuits and Systems (ISSCS) ◽

10.1109/isscs.2017.8034947 ◽

2017 ◽

Author(s):

Daniel Foty

Keyword(s):

Low Power ◽

Cmos Circuits ◽

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Piecewise-linear timing delay modeling for digital CMOS circuits

IEEE Transactions on Circuits and Systems ◽

10.1109/31.7609 ◽

1988 ◽

Vol 35 (10) ◽

pp. 1330-1334 ◽

Author(s):

A.-C. Deng

Keyword(s):

Piecewise Linear ◽

Cmos Circuits ◽

Digital Cmos ◽

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Resonance circuits for adiabatic circuits

Advances in Radio Science ◽

10.5194/ars-1-223-2003 ◽

2003 ◽

Vol 1 ◽

pp. 223-228

Author(s):

C. Schlachta ◽

M. Glesner

Keyword(s):

Energy Storage ◽

Power Consumption ◽

Charge Transport ◽

Cmos Circuits ◽

Digital Cmos ◽

Storage Element

Abstract. One of the possible techniques to reduces the power consumption in digital CMOS circuits is to slow down the charge transport. This slowdown can be achieved by introducing an inductor in the charging path. Additionally, the inductor can act as an energy storage element, conserving the energy that is normally dissipated during discharging. Together with the parasitic capacitances from the circuit a LCresonant circuit is formed.

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Analytical semi-empirical model for SER sensitivity estimation of deep-submicron CMOS circuits

11th IEEE International On-Line Testing Symposium ◽

10.1109/iolts.2005.15 ◽

2005 ◽

Author(s):

T. Heijmen

Keyword(s):

Empirical Model ◽

Deep Submicron ◽

Cmos Circuits ◽

Sensitivity Estimation ◽

Submicron Cmos ◽

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Design and realization of a 2.4 Gbps - 3.2 Gbps clock and data recovery circuit using deep-submicron digital CMOS technology

IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings. ◽

10.1109/soc.2003.1241471 ◽

2004 ◽

Author(s):

Z.O. Gursoy ◽

Y. Leblebici

Keyword(s):

Clock And Data Recovery ◽

Cmos Technology ◽

Deep Submicron ◽

Data Recovery ◽

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