The digital front-end electronics for the space-borne INTEGRAL-SPI experiment: ASIC design, design for test strategies and self-test facilities

2005 ◽  
Author(s):  
B. Cordier ◽  
M. Donati ◽  
R. Duc ◽  
J.L. Fallou ◽  
T. Larque ◽  
...  
Keyword(s):  
Design For Test ◽  
Asic Design ◽  
Test Strategies ◽  
Front End ◽  
Self Test

The digital front-end electronics for the space-borne INTEGRAL-SPI experiment: ASIC design, design for test strategies and self-test facilities

2002 ◽  
Vol 49 (5) ◽  
pp. 2492-2496 ◽  
Author(s):  
M. Mur ◽  
B. Cordier ◽  
M. Donati ◽  
R. Duc ◽  
J.L. Fallon ◽  
...  
Keyword(s):  
Design For Test ◽  
Asic Design ◽  
Test Strategies ◽  
Front End ◽  
Self Test

Weighted Cellular Automata Design for Test Pattern Generator Based on Genetic Algorithm

2013 ◽  
Vol 273 ◽  
pp. 840-844 ◽  
Author(s):  
En Min Tan ◽  
Qing Qing Li ◽  
Ji Gang Jiang
Keyword(s):  
Cellular Automata ◽  
Test Pattern ◽  
Pattern Generator ◽  
Fault Coverage ◽  
Test Design ◽  
Design For Test ◽  
Test Length ◽  
Vlsi Test ◽  
Self Test ◽  
Built In Self Test

In built-in self-test design for VLSI, test pattern generator should satisfy some multi-targets, such as test length, fault coverage and test consumption, etc. A one-dimension hybrid cellular automata (CA) is used as the core of test pattern generator, with an optimization of its rules based on multi-objectives evolution algorithm. A certain rule which selected from the optimized rule set is adopted to form the weighted cellular automata, by the using of verilog HDL. Experiment results was obtained by simulation of some ISCAS’8n built-in self-test design for VLSI, test pattern generator should satisfy some multi-targets, such as test le5 benchmark circuits, and indicated that the test length was reduced obviously (at a ratio above 60%), without losing fault coverage (within a discrepancy of 3%); moreover, the power consumption would be decreased correspondingly.

AN IMPROVED RULE-BASED DUMMY METAL FILL METHOD FOR 65 NM ASIC DESIGN

2013 ◽  
Vol 22 (04) ◽  
pp. 1350021
Author(s):  
XIAOMING CHEN ◽  
LING XIN ◽  
JIANWEI ZHANG ◽  
SONGSONG LI
Keyword(s):  
Oxide Thickness ◽  
File Size ◽  
Rule Based ◽  
Asic Design ◽  
Model Based ◽  
Front End ◽  
Small Capacitance ◽  
Capacitance Variation ◽  
Deep Submicrometer ◽  
Scale Design

Chemical-mechanical polishing (CMP) is an essential process in deep-submicrometer LSI manufacturing to achieve Chip's planarization. It includes two processes: back-end-of-line (BEOL) and front-end-of-line (FEOL). This paper focuses on the problem of BEOL in 65 nm copper process. Although model-based dummy metal fill has become a tendency recently, the proposed improved rule-based dummy fill is appropriate still. A middle scale design is used for simulation. The metal density, oxide thickness, copper thickness, capacitance variation and variation of layout data size were investigated. The results show that improved rule-based dummy fill and model-based dummy fill have the same planarization, and proposed method has small capacitance variation. The GDS file size of the proposed rule-based fill is less than the model-based fill's.

A front-end ASIC design for non-uniformity correction

2008 ◽  
Author(s):  
X. Shen ◽  
R. J. Ding ◽  
J. M. Lin ◽  
F. Liu
Keyword(s):  
Asic Design ◽  
Front End

scholarly journals Spectral Signature Analysis – BIST for RF Front-Ends

2003 ◽  
Vol 1 ◽  
pp. 155-160 ◽  
Author(s):  
D. Lupea ◽  
U. Pursche ◽  
H.-J. Jentschel
Keyword(s):  
Frequency Response ◽  
Building Blocks ◽  
Test System ◽  
System Level ◽  
Spectral Signature ◽  
Signature Analysis ◽  
Response Evaluation ◽  
Front End ◽  
Rf Front End ◽  
Self Test

Abstract. In this paper, the Spectral Signature Analysis is presented as a concept for an integrable self-test system (Built-In Self-Test – BIST) for RF front-ends is presented. It is based on modelling the whole RF front-end (transmitter and receiver) on system level, on generating of a Spectral Signature and of evaluating of the Signature Response. Because of using multi-carrier signal as the test signature, the concept is especially useful for tests of linearity and frequency response of front-ends. Due to the presented method of signature response evaluation, this concept can be used for Built-In Self-Correction (BISC) at critical building blocks.

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