scholarly journals Spectral Signature Analysis – BIST for RF Front-Ends

2003 ◽  
Vol 1 ◽  
pp. 155-160 ◽  
Author(s):  
D. Lupea ◽  
U. Pursche ◽  
H.-J. Jentschel
Keyword(s):  
Frequency Response ◽  
Building Blocks ◽  
Test System ◽  
System Level ◽  
Spectral Signature ◽  
Signature Analysis ◽  
Response Evaluation ◽  
Front End ◽  
Rf Front End ◽  
Self Test

Abstract. In this paper, the Spectral Signature Analysis is presented as a concept for an integrable self-test system (Built-In Self-Test – BIST) for RF front-ends is presented. It is based on modelling the whole RF front-end (transmitter and receiver) on system level, on generating of a Spectral Signature and of evaluating of the Signature Response. Because of using multi-carrier signal as the test signature, the concept is especially useful for tests of linearity and frequency response of front-ends. Due to the presented method of signature response evaluation, this concept can be used for Built-In Self-Correction (BISC) at critical building blocks.

A current based self-test methodology for RF front-end circuits

2005 ◽  
Vol 36 (12) ◽  
pp. 1091-1102 ◽  
Author(s):  
Anand Gopalan ◽  
Martin Margala ◽  
P.R. Mukund
Keyword(s):  
Test Methodology ◽  
Front End ◽  
Rf Front End ◽  
Self Test ◽  
Front End Circuits ◽  
A Current

Capabilities

2018 ◽  
Author(s):  
Paul F. M. J. Verschure
Keyword(s):  
Building Blocks ◽  
Living Systems ◽  
System Level ◽  
Cognitive Architectures ◽  
Multiple Components ◽  
Perception Action

This chapter introduces the “Capabilities” section of the Handbook of Living Machines. Where the previous section considered building blocks, we recognize that components or modules do not automatically make systems. Hence, in the remainder of this handbook, the emphasis is toward the capabilities of living systems and their emulation in artifacts. Capabilities often arise from the integration of multiple components and thus sensitize us to the need to develop a system-level perspective on living machines. Here we summarize and consider the 14 contributions in this section which cover perception, action, cognition, communication, and emotion, and the integration of these through cognitive architectures into systems that can emulate the full gamut of integrated behaviors seen in animals including, potentially, our own capacity for consciousness.

scholarly journals Design and Implementation of a Farrow-Interpolator-Based Digital Front-End in LTE Receivers for Carrier Aggregation

Electronics ◽  
2021 ◽  
Vol 10 (3) ◽  
pp. 231
Author(s):  
Chester Sungchung Park ◽  
Sunwoo Kim ◽  
Jooho Wang ◽  
Sungkyung Park
Keyword(s):  
Integrated Circuit ◽  
Building Block ◽  
Orthogonal Frequency Division Multiplexing ◽  
Critical Path ◽  
Phase Error ◽  
System Level ◽  
Comb Filter ◽  
Carrier Aggregation ◽  
Path Delay ◽  
Front End

A digital front-end decimation chain based on both Farrow interpolator for fractional sample-rate conversion and a digital mixer is proposed in order to comply with the long-term evolution standards in radio receivers with ten frequency modes. Design requirement specifications with adjacent channel selectivity, inband blockers, and narrowband blockers are all satisfied so that the proposed digital front-end is 3GPP-compliant. Furthermore, the proposed digital front-end addresses carrier aggregation in the standards via appropriate frequency translations. The digital front-end has a cascaded integrator comb filter prior to Farrow interpolator and also has a per-carrier carrier aggregation filter and channel selection filter following the digital mixer. A Farrow interpolator with an integrate-and-dump circuitry controlled by a condition signal is proposed and also a digital mixer with periodic reset to prevent phase error accumulation is proposed. From the standpoint of design methodology, three models are all developed for the overall digital front-end, namely, functional models, cycle-accurate models, and bit-accurate models. Performance is verified by means of the cycle-accurate model and subsequently, by means of a special C++ class, the bitwidths are minimized in a methodic manner for area minimization. For system-level performance verification, the orthogonal frequency division multiplexing receiver is also modeled. The critical path delay of each building block is analyzed and the spectral-domain view is obtained for each building block of the digital front-end circuitry. The proposed digital front-end circuitry is simulated, designed, and both synthesized in a 180 nm CMOS application-specific integrated circuit technology and implemented in the Xilinx XC6VLX550T field-programmable gate array (Xilinx, San Jose, CA, USA).

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