Formal system-on-chip verification: An operation-based methodology and its perspectives in low power design

2013 ◽  
Author(s):  
Joakim Urdahl ◽  
Shrinidhi Udupi ◽  
Dominik Stoffel ◽  
Wolfgang Kunz
Keyword(s):  
Low Power ◽  
Formal System ◽  
Low Power Design ◽  
System On Chip ◽  
On Chip

Low-power hybrid STT/CMOS system-on-chip embedding non-volatile magnetic memory blocks

2015 ◽  
Author(s):  
Christophe Layer ◽  
Kotb Jabeur ◽  
Stephane Gros ◽  
Laurent Becker ◽  
Pierre Paoli ◽  
...  
Keyword(s):  
Low Power ◽  
System On Chip ◽  
Magnetic Memory ◽  
On Chip

A Low-Power High-Efficiency Inductive Link Power Supply for Neural Recording and Stimulation System-on-Chip

2018 ◽  
Vol 14 (1) ◽  
pp. 129-139 ◽  
Author(s):  
Ali H. Hassan ◽  
Hassan Mostafa ◽  
Yehea Ismail ◽  
Ahmed M. Soliman
Keyword(s):  
Low Power ◽  
Power Supply ◽  
High Efficiency ◽  
Neural Recording ◽  
System On Chip ◽  
Inductive Link ◽  
Stimulation System ◽  
On Chip

Low-power system-on-chip architecture for wireless LANs

2004 ◽  
Vol 151 (1) ◽  
pp. 2 ◽  
Author(s):  
L. Bisdounis ◽  
C. Dre ◽  
S. Blionas ◽  
D. Metafas ◽  
A. Tatsaki ◽  
...  
Keyword(s):  
Power System ◽  
Low Power ◽  
Wireless Lans ◽  
System On Chip ◽  
Low Power System ◽  
On Chip

Adaptive circuit block model for power supply noise analysis of low power system-on-chip

2009 ◽  
Author(s):  
Matthias Eireiner ◽  
Doris Schmitt-Landsiedel ◽  
Paul Wallner ◽  
Andreas Schone ◽  
Stephan Henzler ◽  
...  
Keyword(s):  
Power System ◽  
Low Power ◽  
Power Supply ◽  
Noise Analysis ◽  
System On Chip ◽  
Block Model ◽  
Supply Noise ◽  
Low Power System ◽  
Adaptive Circuit ◽  
On Chip

scholarly journals Low power network on chip architectures: A survey

2020 ◽  
Vol 2 (3) ◽  
pp. 158-168
Author(s):  
Muhammad Raza Naqvi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Network Architecture ◽  
High Performance ◽  
State Of The Art ◽  
Network On Chip ◽  
System On Chip ◽  
Power Network ◽  
Network Routers ◽  
On Chip

Mostly communication now days is done through SoC (system on chip) models so, NoC (network on chip) architecture is most appropriate solution for better performance. However, one of major flaws in this architecture is power consumption. To gain high performance through this type of architecture it is necessary to confirm power consumption while designing this. Use of power should be diminished in every region of network chip architecture. Lasting power consumption can be lessened by reaching alterations in network routers and other devices used to form that network. This research mainly focusses on state-of-the-art methods for designing NoC architecture and techniques to reduce power consumption in those architectures like, network architecture, network links between nodes, network design, and routers.

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