QoS Improvement Using In-Network Caching Based on Clustering and Popularity Heuristics in CCN

Content-Centric Networking (CCN) has emerged as a potential Internet architecture that supports name-based content retrieval mechanism in contrast to the current host location-oriented IP architecture. The in-network caching capability of CCN ensures higher content availability, lesser network delay, and leads to server load reduction. It was observed that caching the contents on each intermediate node does not use the network resources efficiently. Hence, efficient content caching decisions are crucial to improve the Quality-of-Service (QoS) for the end-user devices and improved network performance. Towards this, a novel content caching scheme is proposed in this paper. The proposed scheme first clusters the network nodes based on the hop count and bandwidth parameters to reduce content redundancy and caching operations. Then, the scheme takes content placement decisions using the cluster information, content popularity, and the hop count parameters, where the caching probability improves as the content traversed toward the requester. Hence, using the proposed heuristics, the popular contents are placed near the edges of the network to achieve a high cache hit ratio. Once the cache becomes full, the scheme implements Least-Frequently-Used (LFU) replacement scheme to substitute the least accessed content in the network routers. Extensive simulations are conducted and the performance of the proposed scheme is investigated under different network parameters that demonstrate the superiority of the proposed strategy w.r.t the peer competing strategies.

Low power network on chip architectures: A survey

Mostly communication now days is done through SoC (system on chip) models so, NoC (network on chip) architecture is most appropriate solution for better performance. However, one of major flaws in this architecture is power consumption. To gain high performance through this type of architecture it is necessary to confirm power consumption while designing this. Use of power should be diminished in every region of network chip architecture. Lasting power consumption can be lessened by reaching alterations in network routers and other devices used to form that network. This research mainly focusses on state-of-the-art methods for designing NoC architecture and techniques to reduce power consumption in those architectures like, network architecture, network links between nodes, network design, and routers.

An Effective Fairness Scheme for Named Data Networking

Named data networking (NDN) is a revolutionary approach to cater for modern and future Internet usage trends. The advancements in web services, social networks and cloud computing have shifted Internet utilization towards information delivery. Information-centric networking (ICN) enables content-awareness in the network layer and adopts name-based routing through the NDN architecture. Data delivery in NDN is receiver-driven pull-based and governed by requests (interests) sent out by the receiver. The ever-increasing share of high-volume media streams traversing the Internet due to the popularity and availability of video-streaming services can put a strain on network resources and lead to congestion. Since most congestion control techniques proposed for NDN are receiver-based and rely on the users to adjust their interest rates, a fairness scheme needs to be implemented at the intermediate network nodes to ensure that “rogue” users do not monopolize the available network resources. This paper proposes a fairness-based active queue management at network routers which performs per-flow interest rate shaping in order to ensure fair allocation of resources. Different congestion scenarios for both single path and multipath network topologies have been simulated to test the effectiveness of the proposed fairness scheme. Performance of the scheme is evaluated using Jain’s fairness index as a fairness metric.

Low Power Implementation Of Ternary Content Addressable Memory (TCAM)

In network routers, Ternary Content Addressable Memory (TCAM)[1] based search engines take an important role. One of the improved versions of Content Addressable Memory (CAM) is TCAM. For high speed and broader searching operation TCAM is used. Unlike normal CAM, TCAM has 3 logic states: 0, 1, ‘X’. In TCAM within one single clock cycle, search operation can be performed. That is why it is called special type of memory. Also, quick search ability is one of the popular features of TCAM. To compare the search and stored data, TCAM array acts parallel in every location. But high power dissipation is the main disadvantage of TCAM. To overcome this power dissipation in this paper we proposed a low power TCAM implementation by using Reversible logic.[2] Reversible logic has less heat dissipating characteristics property with respect to irreversible gate. Also, Reversible logic has ultra-low power characteristics feature. In recent past it has been proved that reversible gates can implement any Boolean function.

Dynamic Energy Reduction in TCAM Match-Line Sensing Using Charge-Sharing and Positive Feedback

Network routers use ternary content addressable memory (TCAM) for high-speed table look-up. A match-line (ML) sensing scheme for TCAM combining charge-sharing and positive feedback is presented. The objective is to simplify the ML sense amplifier (MLSA) of existing charge-sharing scheme while reducing ML energy consumption during look-up. The look-up has been performed in two steps. In the first step, a segment of each TCAM word is compared with the search key to detect large percentage of the mismatched words. The detected mismatched words are deactivated in the second step to reduce energy consumption. In the second step, the charge stored in a matched ML first segment is shared with second ML segment. Use of positive feedback in this step makes the MLSA circuit simple. Post-layout simulations implemented using 180[Formula: see text]nm 1.8[Formula: see text]V CMOS logic have been performed. In addition to lower scheme complexity and 16.5% reduction in circuit area, the proposed scheme provides dynamic energy saving up to 5.5% and peak power reduction of 52% compared to existing state-of-the-art charge-sharing technique.