High-speed silicon-germanium photodetectors for chip-scale photonic interconnects

Author(s):  
D. Benedikovic ◽  
G. Aubin ◽  
L. Virot ◽  
J.-M. Hartmann ◽  
F. Amar ◽  
...  
1998 ◽  
Vol 45 (9) ◽  
pp. 2085-2088 ◽  
Author(s):  
Jyh-Jier Ho ◽  
Y.K. Fang ◽  
Kun-Hsien Wu ◽  
W.T. Hsieh ◽  
S.C. Huang ◽  
...  

2021 ◽  
Vol 255 ◽  
pp. 01002
Author(s):  
Daniel Benedikovic ◽  
Leopold Virot ◽  
Guy Aubin ◽  
Jean-Michel Hartmann ◽  
Farah Amar ◽  
...  

Optical photodetectors are at the forefront of photonic research since the rise of integrated optics. Photodetectors are fundamental building blocks for chip-scale optoelectronics, enabling conversion of light into an electrical signal. Such devices play a key role in many surging applications from communication and computation to sensing, biomedicine and health monitoring, to name a few. However, chip integration of optical photodetectors with improved performances is an on-going challenge for mainstream optical communications at near-infrared wavelengths. Here, we present recent advances in heterostructured silicon-germanium-silicon p-i-n photodetectors, enabling high-speed detection on a foundry-compatible monolithic platform.


1982 ◽  
Vol 21 (Part 1, No. 11) ◽  
pp. 1559-1565 ◽  
Author(s):  
Katsumi Murase ◽  
Yoshihito Amemiya ◽  
Yoshihiko Mizushima

2005 ◽  
Vol 15 (03) ◽  
pp. 477-495 ◽  
Author(s):  
SHANTHI PAVAN ◽  
MAURICE TARSIA ◽  
STEFFEN KUDSZUS ◽  
DAVID PRITZKAU

We present design considerations for high speed high swing differential modulator drivers in SiGe BiCMOS technology. Trade-offs between lumped and distributed designs, and linear and limiting amplifiers are examined. The design of a 6 V output modulator driver is discussed in detail. The driver features a unique bias generation and distribution circuit that enables low power-supply operation. Simulation results and measurements are given.


1994 ◽  
Vol 270 (3) ◽  
pp. 62-67 ◽  
Author(s):  
Bernard S. Meyerson
Keyword(s):  

2003 ◽  
Vol 13 (01) ◽  
pp. 221-237
Author(s):  
KARL E. FRITZ ◽  
BARBARA A. RANDALL ◽  
GREGG J. FOKKEN ◽  
MICHAEL J. DEGERSTROM ◽  
MICHAEL J. LORSUNG ◽  
...  

Under the auspices of Defense Advanced Research Project Agency's Microsystems Technology Office (DARPA/MTO) Low Power Electronics Program, the Mayo Foundation Special Purpose Processor Development Group is exploring ways to reduce circuit power consumption, while maintaining or increasing functionality, for existing military systems. Applications presently being studied include all-digital radar receivers, electronic warfare receivers, and other types of digital signal processors. One of the integrated circuit technologies currently under investigation to support such military systems is the IBM Corporation silicon germanium (SiGe) BiCMOS process. In this paper, design methodology, simulations and test results from demonstration circuits developed for these applications and implemented in the IBM SiGe BiCMOS 5HP (50 GHz fT HBTs with 0.5 μm CMOS) and 7HP (120 GHz fT HBTs with 0.18 μm CMOS) technologies will be presented.


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