A Low-Noise 2.5GHz Direct-Conversion Receiver Frond-End with Low-Distortion Baseband Filters

Author(s):  
Osama Shana'a
Electronics ◽  
2020 ◽  
Vol 9 (9) ◽  
pp. 1369
Author(s):  
Dongquan Huo ◽  
Luhong Mao ◽  
Liji Wu ◽  
Xiangmin Zhang

Direct conversion receiver (DCR) architecture is a promising candidate in the radio frequency (RF) front end because of its low power consumption, low cost and ease of integration. However, flicker noise and direct current (DC) offset are large issues. Owing to the local oscillator (LO) frequency, which is half of the RF frequency, and the absence of a DC bias current that introduces no flicker noise, the subharmonic passive mixer (SHPM) core topology front end overcomes the shortcoming effectively. When more and more receivers (RX) and transmitters (TX) are integrated into one chip, the linearity of the receiver front end becomes a very important performer that handles the TX and RX feedthrough. Another reason for the requirement of good linearity is the massive electromagnetic interference that exists in the atmosphere. This paper presents a linearity-improved RF front end with a feedforward body bias (FBB) subharmonic mixer core topology that satisfies modern RF front end demands. A novel complementary derivative superposition (DS) method is presented in low noise amplifier (LNA) design to cancel both the third- and second-order nonlinearities. To the best knowledge of the authors, this is the first time FBB technology is used in the SHPM core to improve linearity. A Volterra series is introduced to provide an analytical formula for the FBB of the SHPM core. The design was fabricated in a 0.13 μm complementary metal oxide semiconductor (CMOS) process with a chip area of 750 μm × 1270 μm. At a 2.4 GHz working frequency, the measurement result shows a conversion gain of 36 dB, double side band (DSB) noise figure (NF) of 6.8 dB, third-order intermodulation intercept point (IIP3) of 2 dBm, LO–RF isolation of 90 dB and 0.8 mW DC offset with 14.4 mW power consumption at 1.2 V supply voltage. These results exhibit better LO–RF feedthrough and DC offset, good gain and NF, moderate IIP3 and the highest figure of merit compared to the state-of-the-art publications.


2014 ◽  
Vol 14 (5) ◽  
pp. 1357-1363 ◽  
Author(s):  
Zoltan Karasz ◽  
Richard Fiath ◽  
Peter Foldesy ◽  
Angel Rodriguez Vazquez

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1966
Author(s):  
Yiming Han ◽  
Fengjie Wang ◽  
Jiarui Liu ◽  
Zhiyu Wang ◽  
Faxin Yu

To improve the linearity of direct conversion receivers (DCRs), two high-linearity methods for high second-order intercept points (IP2s) and high third-order intercept points (IP3s) are proposed. To improve IP3s, a transconductance equalization technique for a complementary input operational amplifier (OPAMP) is proposed in an active-RC low-pass filter (LPF), while a digital-analog hybrid DC offset calibration (DCOC) method is proposed to improve IP2s. For one thing, the proposed transconductance equalization technique employs a pair of resistors to guarantee high voltage gain for an OPAMP with two-stage Miller topology under a high-input voltage swing to improve linearity with little deterioration of the noise performance. For another, during the DCOC method, the low-noise amplifier is turned off and replaced by an equivalent resistance of the output impedance of the low-noise amplifier to ensure the accuracy and effectiveness of the DCOC method. Fabricated in 40-nm CMOS technology, the receiver with proposed methods can realize a noise figure of 2.6–3.5 dB in the full frequency band, with an OIP3 of 28 dBm, an IM2 more than 70 dBc, and a remaining DC of −53.2 dBm under the total voltage gain of 60 dB.


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