Driving lessons for a low noise, low distortion, 16-bit, 1Msps SAR ADC

2015 ◽  
pp. 715-716
Author(s):  
Guy Hoover
Keyword(s):  
Low Noise ◽  
Sar Adc ◽  
Low Distortion

A Linearity Improved 10-bit 120-MS/s 1.5 mW SAR ADC with High-Speed and Low-Noise Dynamic Comparator Technique

2019 ◽  
Vol 29 (06) ◽  
pp. 2050084
Author(s):  
Daiguo Xu ◽  
Hequan Jiang ◽  
Dongbin Fu ◽  
Xiaoquan Yu ◽  
Shiliu Xu ◽  
...  
Keyword(s):  
High Speed ◽  
Cmos Technology ◽  
Low Noise ◽  
Sar Adc ◽  
Dynamic Comparator ◽  
Analog To Digital ◽  
Input Noise ◽  
Clock Feedthrough ◽  
Threshold Voltages ◽  
Coupled Technique

This paper presents a linearity improved 10-bit 120-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with high-speed and low-noise dynamic comparator. A gate cross-coupled technique is introduced in boost sampling switch, the clock feedthrough effect is compensated without extra auxiliary switch and the linearity of sampling switch is enhanced. Further, substrate voltage boost technique is proposed, the absolute values of threshold voltage and equivalent impedances of MOSFETs are both depressed. Consequently, the delay of comparator is also reduced. Moreover, the reduction of threshold voltages for input MOSFETs could bring higher transconductance and lower equivalent input noise. To demonstrate the proposed techniques, a design of SAR ADC is fabricated in 65-nm CMOS technology, consuming 1.5[Formula: see text]mW from 1[Formula: see text]V power supply with a SNDR [Formula: see text][Formula: see text]dB and SFDR [Formula: see text][Formula: see text]dB. The proposed ADC core occupies an active area of 0.021[Formula: see text]mm2, and the corresponding FoM is 24.4 fJ/conversion-step with Nyquist frequency.

Tunable Low Noise Amplifier Implementation With Low Distortion Pseudo-Resistance for in Vivo Brain Activity Measurement

2014 ◽  
Vol 14 (5) ◽  
pp. 1357-1363 ◽  
Author(s):  
Zoltan Karasz ◽  
Richard Fiath ◽  
Peter Foldesy ◽  
Angel Rodriguez Vazquez
Keyword(s):  
Brain Activity ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Activity Measurement ◽  
Low Distortion ◽  
Noise Amplifier

A Linearity-Enhanced 10-Bit 160-MS/s SAR ADC With Low-Noise Comparator Technique

2019 ◽  
Vol 27 (9) ◽  
pp. 1990-1997 ◽  
Author(s):  
Daiguo Xu ◽  
Hequan Jiang ◽  
Lei Qiu ◽  
Xiaoquan Yu ◽  
Jianan Wang ◽  
...  
Keyword(s):  
Low Noise ◽  
Sar Adc

Low noise, low-distortion front-end IC for 1.1-V paging receiver

1991 ◽  
Vol 37 (3) ◽  
pp. 578-584 ◽  
Author(s):  
S. Tanaka ◽  
A. Nakajima ◽  
A. Nakagoshi ◽  
K. Washio ◽  
K. Takei ◽  
...  
Keyword(s):  
Low Noise ◽  
Front End ◽  
Low Distortion

scholarly journals Modeling of High-Resolution Data Converter: Two-Step Pipelined-SAR ADC based on ISDM

Electronics ◽  
2020 ◽  
Vol 9 (1) ◽  
pp. 137 ◽  
Author(s):  
Bo Gao ◽  
Xin Li ◽  
Jie Sun ◽  
Jianhui Wu
Keyword(s):  
High Resolution ◽  
Low Noise ◽  
Sar Adc ◽  
Total Power ◽  
Cmos Process ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Signal To Noise ◽  
Analog To Digital ◽  
High Bandwidth

The features of high-resolution and high-bandwidth are in an increasing demand considering to the wide range application fields based on high performance data converters. In this paper, a modeling of high-resolution hybrid analog-to-digital converter (ADC) is proposed to meet those requirements, and a 16-bit two-step pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with first-order continuous-time incremental sigma-delta modulator (ISDM) assisted is presented to verify this modeling. The combination of high-bandwidth two-step pipelined-SAR ADC with low noise ISDM and background comparator offset calibration can achieve higher signal-to-noise ratio (SNR) without sacrificing the speed and plenty of hardware. The usage of a sub-ranging scheme consists of a coarse SAR ADC followed by an fine ISDM, can not only provide better suppression of the noise added in 2nd stage during conversion but also alleviate the demands of comparator’s resolution in both stages for a given power budget, compared with a conventional Pipelined-SAR ADC. At 1.2 V/1.8 V supply, 33.3 MS/s and 16 MHz input sinusoidal signal in the 40 nm complementary metal oxide semiconductor (CMOS) process, the post-layout simulation results show that the proposed hybrid ADC achieves a signal-to-noise distortion ratio (SNDR) and a spurious free dynamic range (SFDR) of 86.3 dB and 102.5 dBc respectively with a total power consumption of 19.2 mW.

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