Via-Free Interconnection in Quasi-Hermetic Wafer-Level Packaging for RF-MEMS Applications and 3D Integration

Author(s):  
Alain Phommahaxay ◽  
Gaelle Lissorgues ◽  
Lionel Rousseau ◽  
Vincent Perrais ◽  
Frederic Marty ◽  
...  
2010 ◽  
Vol 2010 (1) ◽  
pp. 000325-000332 ◽  
Author(s):  
Alan Huffman ◽  
Philip Garrou

As IC scaling continues to shrink transistors, the increased number of circuits per chip requires more I/O per unit area (Rent's rule). High I/O count, the need for smaller form factors and the need for better electrical performance drove the technological change towards die being interconnected (assembled) by area array techniques. This review will examine this evolution from die wire bonded on lead frames to flip chip die in wafer level or area array packages and discuss emerging technologies such as copper pillar bumps, fan out packaging, integrated passives, and 3D integration..


Author(s):  
Qian Wang ◽  
Sung Hoon Choa ◽  
Woon Bae Kim ◽  
Jun Sik Hwang ◽  
Suk Jin Ham ◽  
...  

Author(s):  
M. David Henry ◽  
Travis Young ◽  
Andrew E. Hollowell ◽  
Matt Eichenfield ◽  
Roy H. Olsson

Author(s):  
M. David Henry ◽  
K. Douglas Greth ◽  
Janet Nguyen ◽  
Christopher D. Nordquist ◽  
Randy Shul ◽  
...  

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