Hermetic wafer-level packaging for RF MEMs: Effects on resonator performance

In this paper, the development of wafer level packaging of radio frequency (RF) microelectromechanical system (MEMS) is reported. The packaging process consists of wafer bonding, wafer thinning, via etching, plating, under-bump-metallization (UBM) and bumping processes. 6-inch Si and glass wafers are used in the study. RF MEMS devices are fabricated on Si wafers and sandwiched between Si and glass cap wafers. To maintain the pressure balance between the cavities and outside world after bonding process, Si and glass wafers are anodically bonded at a pressure of 2 bar and a bonding temperature of 400 °C. The cavities are hermetically sealed. The glass wafer of the bonded pair is thinned down to 100 μm using mechanical polishing and chemical etching, the good uniformity of the wafer thickness is maintained with etching process. A layer of Cr/Au is sputtered and patterned as the hard mask for glass via etching process. Via holes with undercut closer to the etching depth are formed in HF+HNO3 acid. After stripping the metal mask, a seed layer of TiW/Cu is deposited using sputtering and plating processes. TiW layer is used to enhance the adhesion of metal and glass. With the completion of the re-routing and via metallization processes, benzocyclobutene (BCB) photoresist is used to planarize via holes and opened for UBM process. Finally, the packaged devices can be assembled using flip chip approach.

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Advanced Wafer Level Packaging of RF-MEMS with RDL Inductor

International Symposium on Microelectronics ◽

10.4071/isom-2016-wa33 ◽

2016 ◽

Vol 2016 (1) ◽

pp. 000185-000189 ◽

Cited By ~ 1

Author(s):

Paul Castillou ◽

Roberto Gaddi ◽

Rob van Kampen ◽

Yaojian Lin ◽

Babak Jamshidi ◽

...

Keyword(s):

Rf Mems ◽

Data Access ◽

Silicon On Insulator ◽

Electrical Performance ◽

Battery Life ◽

Wafer Level ◽

Integrated Inductor ◽

Wafer Level Packaging ◽

Mems Technology ◽

Rf Performance

Abstract The market for portable and mobile data access devices that are wirelessly connected to the cloud anytime and anywhere is exploding. The trend to access any network from anywhere is driving increased functional convergence in the radio, which translates into increased packaging complexity and sophistication. This is creating unprecedented demand for RF components providing more integration- in smaller package sizes. There are exciting interconnect technologies in wafer level packaging such as wafer level chip scale packaging (WLCSP) or fan-out wafer level packaging (FO-WLP) solutions such as embedded Wafer Level Ball Grid Array (eWLB) to meet these needs. One of the most promising solutions to enable the required RF performance levels in mobile and wearable devices is the use of RF MEMS Tuners. Mobile original equipment manufacturers (OEMs) are rapidly adopting antenna tuning solutions to be able to provide the required signal strength across the large number of LTE spectrum bands used globally. With RF MEMS technology now maturing, the biggest challenge to address the fast growing opportunity was to find a suitable packaging technology that can deliver RF MEMS tuners in the smallest possible form factor, while maintaining the excellent performance characteristics of the RF MEMS technology. After careful analysis, an eWLB/FO-WLP package was adopted and released to volume production in 2015. The commercial eWLB/FO-WLP RF MEMS tuners outperform traditional RF silicon-on-insulator (SOI) switch-based antenna tuning solutions, resulting in much higher data rates (up to 2×) and improved battery life (up to 40%). Redistribution layers (RDL) in eWLB are utilized for higher electrical performance and complex routing to meet electrical requirements. The ability to utilize embedded passives in a multi-layer eWLB structure provides a number of advantages including cost reduction, footprint reduction and increased reliability. Inductors in eWLB offer significantly better performance compared to inductors in standard on-chip technologies. In this paper, we examine the WLCSP and eWLB packaging assembly flow, solutions to RF design challenges as well as characterization of RF performance. Further improvement of the quality factor of the integrated inductor and capacitors by using low-loss thin-film dielectrics and molding compound in eWLB will be reported as well. Package level reliability test results will also be presented in this paper.

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