28 Gbps Bang-Bang CDR for 100G PSM4 with Independently Tunable Proportional and Integral Parameters of the Loop Filter in $0.25\ \mu \mathrm{m}$ Photonic BiCMOS Technology

Author(s):  
Mohammed Iftekhar ◽  
Sergiy Gudyriev ◽  
J. Christoph Scheytt
2012 ◽  
Vol 4 (4) ◽  
pp. 441-446 ◽  
Author(s):  
Atheer Barghouthi ◽  
Marcu Hellfeld ◽  
Corrado Carta ◽  
Frank Ellinger

The design of a 61.44 GHz integrated Phase-locked loop (PLL) on a 180 GHz BiCMOS technology is presented. The PLL was optimized for a very fast settling time of 4 µs as required by the system specifications. Because the receiver is using a carrier recovery circuit that can follow the slow changes of the carrier such as phase noise, the sensitivity of the bit error rate to phase noise at the receiver end is very low. As a result, to achieve the required dynamic behavior, the phase noise performance could be sacrificed and the loop bandwidth was increased until the needed settling time was achieved, while taking the suppression of the reference spurs into consideration. Capacitor multiplication was used to enable the integration of the loop filter (LF) on chip and the effect of the capacitor multiplier on the total PLL phase noise performance was quantified and evaluated. In addition, a very close matching between the measured and simulated phase noise of the system was achieved. The PLL consumes a power of 200 mW from 2 and 3 V supply voltages, while delivering a differential output power of −7 dBm, sufficient to drive the following I/Q modulator without additional amplification.


2021 ◽  
Vol 68 (4) ◽  
pp. 1439-1445
Author(s):  
Hanbin Ying ◽  
Jeffrey W. Teng ◽  
John D. Cressler

Author(s):  
Zhijie Huang ◽  
Jun Sun ◽  
Xiaopeng Guo ◽  
Mingyu Shang

Author(s):  
Baoling Guo ◽  
Seddik Bacha ◽  
Mazen Alamir ◽  
Julien Pouget

AbstractAn extended state observer (ESO)-based loop filter is designed for the phase-locked loop (PLL) involved in a disturbed grid-connected converter (GcC). This ESO-based design enhances the performances and robustness of the PLL, and, therefore, improves control performances of the disturbed GcCs. Besides, the ESO-based LF can be applied to PLLs with extra filters for abnormal grid conditions. The unbalanced grid is particularly taken into account for the performance analysis. A tuning approach based on the well-designed PI controller is discussed, which results in a fair comparison with conventional PI-type PLLs. The frequency domain properties are quantitatively analysed with respect to the control stability and the noises rejection. The frequency domain analysis and simulation results suggest that the performances of the generated ESO-based controllers are comparable to those of the PI control at low frequency, while have better ability to attenuate high-frequency measurement noises. The phase margin decreases slightly, but remains acceptable. Finally, experimental tests are conducted with a hybrid power hardware-in-the-loop benchmark, in which balanced/unbalanced cases are both explored. The obtained results prove the effectiveness of ESO-based PLLs when applied to the disturbed GcC.


Author(s):  
Abdul Ali ◽  
Wael Abdullah Ahmad ◽  
Herman Jalli Ng ◽  
Dietmar Kissinger ◽  
Franco Giannini ◽  
...  

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