A novel structure for optimization of switching speed in nanoscale Double Gate Tunnel FET

2008 IEEE International Conference on Semiconductor Electronics ◽

10.1109/smelec.2008.4770374 ◽

2008 ◽

Author(s):

Vadizadeh Mahdi ◽

Fathipour Morteza

Keyword(s):

Double Gate ◽

Switching Speed ◽

Tunnel Fet ◽

Novel Structure

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A Novel Structure of Double-Gate Tunnel FET with Extended Back Gate for Improved Device Performances

2019 2nd International Conference on Innovations in Electronics, Signal Processing and Communication (IESC) ◽

10.1109/iespc.2019.8902442 ◽

2019 ◽

Author(s):

Chandan K. Pandey ◽

Saurabh Chaudhury

Keyword(s):

Double Gate ◽

Back Gate ◽

Tunnel Fet ◽

Novel Structure

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Investigation of Homo and Hetero-Junction Double-Gate Tunnel-FET-Based Adiabatic Inverter Circuits

IETE Journal of Research ◽

10.1080/03772063.2020.1859951 ◽

2020 ◽

pp. 1-9

Author(s):

M. Pown ◽

S. Sandeep ◽

B. Lakshmi

Keyword(s):

Double Gate ◽

Tunnel Fet

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Double gate vertical tunnel FET for hybrid CMOS-TFET based low standby power logic circuits

2013 Annual International Conference on Emerging Research Areas and 2013 International Conference on Microelectronics, Communications and Renewable Energy ◽

10.1109/aicera-icmicr.2013.6575992 ◽

2013 ◽

Cited By ~ 5

Author(s):

Abhishek Mishra ◽

Manisha Pattanaik ◽

Varun Sharma

Keyword(s):

Logic Circuits ◽

Double Gate ◽

Tunnel Fet ◽

Hybrid Cmos ◽

Standby Power

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A 2-D Double Gate Heterojunction Tunnel-FET Based on AlGaSb/InAs: Analytical Analysis on Electric Field and Capacitance

10.1109/icsct53883.2021.9642561 ◽

2021 ◽

Author(s):

Sunjida Sultana ◽

Md. Tawfiq Amin ◽

Twisha Titirsha

Keyword(s):

Electric Field ◽

Double Gate ◽

Analytical Analysis ◽

Tunnel Fet

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Double Gate Tunnel FET Versus Double Gate MOSFET: Electrical Properties Comparison

Lecture Notes in Electrical Engineering - Electronic Systems and Intelligent Computing ◽

10.1007/978-981-15-7031-5_75 ◽

2020 ◽

pp. 791-803

Author(s):

Menka Yadav

Keyword(s):

Electrical Properties ◽

Double Gate ◽

Tunnel Fet ◽

Double Gate Mosfet

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Impact of encroaching length and taper on double gate tunnel FET performance using TCAD simulations

2013 International Conference on Circuits, Power and Computing Technologies (ICCPCT) ◽

10.1109/iccpct.2013.6528880 ◽

2013 ◽

Author(s):

S.Shinly Swarna Sugi ◽

K.K. Nagarajan ◽

R. Srinivasan

Keyword(s):

Double Gate ◽

Tunnel Fet ◽

Tcad Simulations

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A charge-based capacitance model for double-gate hetero-gate-dielectric tunnel FET

Superlattices and Microstructures ◽

10.1016/j.spmi.2020.106748 ◽

2020 ◽

pp. 106748

Author(s):

Sarabjeet Kaur ◽

Ashish Raman ◽

Rakesh Kumar Sarin

Keyword(s):

Gate Dielectric ◽

Double Gate ◽

Tunnel Fet ◽

Capacitance Model ◽

A Charge

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Using low-k oxide for reduction of leakage current in Double Gate Tunnel FET

2009 10th International Conference on Ultimate Integration of Silicon ◽

10.1109/ulis.2009.4897595 ◽

2009 ◽

Cited By ~ 2

Author(s):

Mahdi Vadizadeh ◽

Morteza Fathipour

Keyword(s):

Leakage Current ◽

Double Gate ◽

Tunnel Fet ◽

Low K

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Double-Gate Tunnel FET With High-$\kappa$ Gate Dielectric

IEEE Transactions on Electron Devices ◽

10.1109/ted.2007.899389 ◽

2007 ◽

Vol 54 (7) ◽

pp. 1725-1733 ◽

Cited By ~ 898

Author(s):

Kathy Boucart ◽

Adrian Mihai Ionescu

Keyword(s):

Gate Dielectric ◽

Double Gate ◽

Tunnel Fet

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Analytically Modeling the Asymmetric Double Gate Tunnel FET

ECS Transactions ◽

10.1149/06605.0193ecst ◽

2015 ◽

Vol 66 (5) ◽

pp. 193-200 ◽

Cited By ~ 2

Author(s):

H. Lv ◽

S. Sato ◽

Y. Omura ◽

A. Mallik

Keyword(s):

Double Gate ◽

Tunnel Fet

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