The Impact of a Paraelectric layer in the FE/DE Stack on Performance of NCFET

<div>In this letter, through TCAD simulations, we show that the introduction of a thin paraelectric (PE) layer between the ferroelectric (FE) and dielectric (DE) layers in an MFIS structure, expands the design space for the FE layer enabling hysteresis-free and steep subthreshold behavior, even with a thicker FE layer. This can be explained by analyzing the FE-PE stack from a capacitance perspective where the thickness of the PE layer in the FE-PE stack has the effect of reducing the FE layer thickness, while also reducing the remnant polarization. Finally, for the same FE-PE-DE stack, analog performance parameters such as $\frac{g_{m}} g_{ds}}$ and $\frac{g_{m}}{I_{d}}$ are analyzed, showing good characteristics over a wide range of gate lengths, at low drain voltages, thus demonstrating applicability for low power applications.</div>

The Impact of a Paraelectric layer in the FE/DE Stack on Performance of NCFET

<div>In this letter, through TCAD simulations, we show that the introduction of a thin paraelectric (PE) layer between the ferroelectric (FE) and dielectric (DE) layers in an MFIS structure, expands the design space for the FE layer enabling hysteresis-free and steep subthreshold behavior, even with a thicker FE layer. This can be explained by analyzing the FE-PE stack from a capacitance perspective where the thickness of the PE layer in the FE-PE stack has the effect of reducing the FE layer thickness, while also reducing the remnant polarization. Finally, for the same FE-PE-DE stack, analog performance parameters such as $\frac{g_{m}} g_{ds}}$ and $\frac{g_{m}}{I_{d}}$ are analyzed, showing good characteristics over a wide range of gate lengths, at low drain voltages, thus demonstrating applicability for low power applications.</div>

The influences of radiation effects on DC/RF performances of Lg=22 nm gate-all-around nanosheet field-effect transistor

In this paper, we carried out detailed TCAD simulations to investigate the radiation effects, e.g., total ionizing dose (TID) and single-event effects (SEEs), on direct current (DC) and radio frequency (RF) characteristics of the gate-all-around (GAA) nanosheet field-effect transistor (FET). The simulation model used is composed of 7-layer stacked GAA nanosheet FET with Lg=22 nm, which was implemented in this study. The open current and the drain-induced barrier lowering of the device are ~ 3mA/μm and 47mV/V, respectively. The results indicate that the TID have little influence on the DC and RF characteristics when the transistor is working in an open state. During the SEEs simulation, we considered three incident directions for the high energy particle, including the lateral direction of the channels, the vertical direction of the channels and the top of the channels. The influence of the particle injecting along the lateral and vertical directions of the channels shows stronger relation with the distance from the incident point compared to the influence of the particle from the top. Besides, the general influence of the particle injecting along the lateral directions of the channels is higher than the other two directions. The total injected charge of the particle injecting along the lateral direction, along the vertical direction and from the top are 3 fC, 1.4 fC and 2.1 fC, respectively. As compared to the FinFET, the GAA nanosheet has superior RF performances and less sensitivity to TID effect. This work can provide a guideline for the GAA nanosheet devices in aerospace and avionic RF applications.

Modeling of GIDL–Assisted Erase in 3–D NAND Flash Memory Arrays and Its Employment in NOR Flash–Based Spiking Neural Networks

Since the very first introduction of three-dimensional (3–D) vertical-channel (VC) NAND Flash memory arrays, gate-induced drain leakage (GIDL) current has been suggested as a solution to increase the string channel potential to trigger the erase operation. Thanks to that erase scheme, the memory array can be built directly on the top of a $$n^+$$ n + plate, without requiring any p-doped region to contact the string channel and therefore allowing to simplify the manufacturing process and increase the array integration density. For those reasons, the understanding of the physical phenomena occurring in the string when GIDL is triggered is important for the proper design of the cell structure and of the voltage waveforms adopted during erase. Even though a detailed comprehension of the GIDL phenomenology can be achieved by means of technology computer-aided design (TCAD) simulations, they are usually time and resource consuming, especially when realistic string structures with many word-lines (WLs) are considered. In this chapter, an analysis of the GIDL-assisted erase in 3–D VC nand memory arrays is presented. First, the evolution of the string potential and GIDL current during erase is investigated by means of TCAD simulations; then, a compact model able to reproduce both the string dynamics and the threshold voltage transients with reduced computational effort is presented. The developed compact model is proven to be a valuable tool for the optimization of the array performance during erase assisted by GIDL. Then, the idea of taking advantage of GIDL for the erase operation is exported to the context of spiking neural networks (SNNs) based on NOR Flash memory arrays, which require operational schemes that allow single-cell selectivity during both cell program and cell erase. To overcome the block erase typical of nor Flash memory arrays based on Fowler-Nordheim tunneling, a new erase scheme that triggers GIDL in the NOR Flash cell and exploits hot-hole injection (HHI) at its drain side to accomplish the erase operation is presented. Using that scheme, spike-timing dependent plasticity (STDP) is implemented in a mainstream NOR Flash array and array learning is successfully demonstrated in a prototype SNN. The achieved results represent an important step for the development of large-scale neuromorphic systems based on mature and reliable memory technologies.

On the compact modelling of Si nanowire and Si nanosheet MOSFETs

In this paper, 3D TCAD simulations are used to show that the electron concentration, current density, and electric field distribution from the interface at the lateral channels and from the top channel to the centre of the silicon wire, in Nanowire and Nanosheet structures, are practically same. This characteristic makes possible to consider that the total channel width for these structures is equal to the perimeter of the transistor sheet, allowing to extend the application of the Symmetric Doped Double-Gate Model (SDDGM) model to Nanowires and Nanosheets MOSFETs, with no need to include new parameters. The Model SDDGM is validated for this application using several measured and simulated structures of Nanowires and Nanosheets transistors, with different aspect ratios of fin width and fin height, showing very good agreement between measured or simulated characteristics and modelled. SDDGM is encoded in Verilog-A language and implemented in SmartSPICE circuit simulator.

Investigation of turn-on performance in 1.2-kV MOS-bipolar devices

In this paper, the turn-on characteristics of 1.2-kV Trench IGBT (TIGBT) and Trench Clustered IGBT (TCIGBT) are investigated through TCAD simulations and experiments. TCIGBT shows much lower turn-on energy loss (Eon) due to higher current gain than an equivalent TIGBT and the negative gate capacitance effect is effectively suppressed in the TCIGBT by its self-clamping feature and PMOS action. In addition, the impact of 3-D scaling rules on the turn-on performance of TIGBT and TCIGBT is analyzed in detail. Simulation results show that scaling rules result in a significant reduction of Eon in both TIGBT and TCIGBT. Furthermore, the experimental results indicate that TCIGBT technology is well suited for high current density operations with low power losses. Compared to the state-of-the-art IGBT technology, an 18 % reduction of total power losses can be achieved by the TCIGBT operated at 300 A/cm2 and 175 °C.

A New Type of Tri-Input TFET with T-Shaped Channel Structure Exhibiting Three-Input Majority Logic Behavior

In this paper, we propose a new type of tri-input tunneling field-effect transistor (Ti-TFET) that can compactly realize the “Majority-Not” logic function with a single transistor. It features an ingenious T-shaped channel and three independent-biasing gates deposited and patterned on its left, right, and upper sides, which greatly enhance the electrostatic control ability between any two gates of all the three gates on the device channel and thus increase its turn-on current. The total current density and energy band distribution in different biasing conditions are analyzed in detail by TCAD simulations. The turn-on current, leakage current, and ratio of turn-on/off current are optimized by choosing appropriate work function and body thickness. TCAD simulation results verify the expected characteristics of the proposed Ti-TFETs in different working states. Ti-TFETs can flexibly be used to implement a logic circuit with a compact style and thus reduce the number of transistors and stack height of the circuits. It provides a new technique to reduce the chip area and power consumption by saving the number of transistors.

A Strategy to Mitigate Single Event Upset in 14 nm CMOS Bulk FinFET Technology

3D TCAD simulations demonstrated that reducing the distance between the well boundary and NMOS or PMOS can mitigate the cross section of Single Event Upset (SEU) in 14 nm CMOS bulk FinFET technology. The competition of charge collection between well boundary and sensitive nodes, the enhanced restore currents and the change of bipolar effect are responsible for the decrease of SEU cross section. Different from Dual-interlock cells (DICE) design, under the presence of enough taps to ensure the rapid recovery of well potential, this approach is more effective under heavy ion irradiation of higher LET. Besides, the feasibility of this method and its effectiveness with feature size scaling down are discussed.

Performance analysis of nanowire and nanosheet NCFETs for future technology nodes

Negative capacitance (NC) effect in nanowire (NW) and nanosheet (NS) field effect transistors (FETs) provide the much-needed voltage scaling in future technology nodes. Here, we present a comparative analysis on the performance of NC-NWFETs and NC-NSFETs through fully calibrated, three-dimensional computer aided design (TCAD) simulations. In addition to single channel NC-NSFETs and NC-NWFETs, those, with vertically stacked NSs and NWs, have been examined for the same layout footprint (LF). Results show that NC-NSFETs can achieve lower subthreshold swing (SS) and higher ON-current (ION ) than NC-NWFET of comparable device dimensions. However, NC-NWFETs show slightly higher ION/IOFF ratio. Negative differential resistance (NDR) is found to be more pronounced in NC-NSFET, enabling these devices to attain a stronger drain-induced-barrier-rising (DIBR) and steeper SS for gate lengths as small as 10 nm. The results presented here can, therefore, provide useful insights for performance optimization of NC-NWFETs and NC-NSFETs, in ultra-scaled and high-density logic applications, for 7 nm and beyond technology nodes.

Electrical сharacteristics study of heterojunction solar сells CdS/CIGS

In this work, we carried out the study of electrical characteristics with two-dimensional numerical analysis by using the Aided Design (TCAD Silvaco) software for CdS/CuInGaSe2 (CIGS) thin solar cells. Their structure is composed of a thin CIGS solar cell in the configuration: ZnO(200 nm)/CdS(50 nm)/CIGS (350 nm)/Mo. Then ZnO is used for conductive oxide contacted transparent front of the cell. For rear contact, the molybdenum (Mo) is used. The layer of the CdS window and the shape of the CIGS absorber is the n-p semiconductor heterojunction. The performance of the cell was evaluated by applying the defects created in the grain joints of polycrystalline CdS and CIGS material and CIGS/CdS interface in the model, and the physical parameters used in the TCAD simulations have been calibrated to reproduce experimental data. The J–V characteristics are simulated under AM1.5 illumination conditions. The conversion efficiency (η) 20.10% has been reached, and the other characteristic parameters have been simulated: the open-circuit voltage (Voc) is 0.68 V, the circuit-current density (Jsc) is equal to 36.91 mA/cm2, and the form factor (FF) is 0.80. The simulation results showed that the molar fraction x of the CIGS layer has an optimal value around 0.31 corresponding to a gap energy of 1.16 eV, this result is in very good agreement with that found experimentally.