Scaling assessment of fully-depleted SOI technology at the 30 nm gate length generation

2002 ◽  
Author(s):  
Vandooren ◽  
Jovanovic ◽  
Egley ◽  
Sadd ◽  
Nguyen ◽  
...  
Keyword(s):  
Gate Length ◽  
Fully Depleted ◽  
Soi Technology

Gate-Length and Drain-Bias Dependence of Band-to-Band Tunneling-Induced Drain Leakage in Irradiated Fully Depleted SOI Devices

2008 ◽  
Vol 55 (6) ◽  
pp. 3259-3264 ◽  
Author(s):  
Farah E. Mamouni ◽  
Sriram K. Dixit ◽  
Ronald D. Schrimpf ◽  
Philippe C. Adell ◽  
Ivan S. Esqueda ◽  
...  
Keyword(s):  
Gate Length ◽  
Fully Depleted ◽  
Band To Band Tunneling ◽  
Drain Bias ◽  
Soi Devices

Large SET Duration Broadening in a Fully-Depleted SOI Technology—Mitigation With Body Contacts

2010 ◽  
Vol 57 (4) ◽  
pp. 1811-1819 ◽  
Author(s):  
V. Ferlet-Cavrois ◽  
D. Kobayashi ◽  
D. McMorrow ◽  
J. R. Schwank ◽  
H. Ikeda ◽  
...  
Keyword(s):  
Large Set ◽  
Fully Depleted ◽  
Soi Technology

Fully Depleted SOI Technology Overview

2017 ◽  
pp. 95-112
Author(s):  
Bich-Yen Nguyen ◽  
Frederic Allibert ◽  
Christophe Maleville ◽  
Walter Schwarzenbach ◽  
Carlos Mazure
Keyword(s):  
Fully Depleted ◽  
Soi Technology

scholarly journals Design and Analysis of Nanoscaled Recessed-S/D SOI MOSFET-Based Pseudo-NMOS Inverter for Low-Power Electronics

2019 ◽  
Vol 2019 ◽  
pp. 1-12 ◽  
Author(s):  
Anjali Priya ◽  
Nilesh Anand Srivastava ◽  
Ram Awadh Mishra
Keyword(s):  
Threshold Voltage ◽  
Propagation Delay ◽  
Silicon On Insulator ◽  
Device Performance ◽  
Gate Length ◽  
Metal Gate ◽  
Short Channel ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Silvaco Atlas

In this paper, a comparative analysis of nanoscaled triple metal gate (TMG) recessed-source/drain (Re-S/D) fully depleted silicon-on-insulator (FD SOI) MOSFET has been presented for the design of the pseudo-NMOS inverter in the nanometer regime. For this, firstly, an analytical modeling of threshold voltage has been proposed in order to investigate the short channel immunity of the studied device and also verified against simulation results. In this structure, the novel concept of backchannel inversion has been utilized for the study of device performance. The threshold voltage has been analyzed by varying the parameters of the device like the ratio of metal gate length and the recessed-source/drain thickness for TMG Re-S/D SOI MOSFET. Drain-induced barrier lowering (DIBL) has also been explored in terms of recessed-source/drain thickness and the metal gate length ratio to examine short channel effects (SCEs). For the exact estimation of results, the comparison of the existing multimetal gate structures with TMG Re-S/D SOI MOSFET has also been taken under study in terms of electrostatic performance, i.e., threshold voltage, subthreshold slope, and on-off current ratio. These structures are investigated with the TCAD numerical simulator from Silvaco ATLAS. Furthermore, for the first time, TMG Re-S/D FD SOI MOSFET-based pseudo-NMOS inverter has been designed to observe the device performance at circuit levels. It has been found that the device offers high noise immunity with optimum switching characteristics, and the propagation delay of the studied circuit is recorded as 0.43 ps.

(Invited) Overview of Fully Depleted SOI Technology and Circuit Benefits

2012 ◽  
Vol 49 (1) ◽  
pp. 41-48 ◽  
Author(s):  
C. Mazure ◽  
B.-Y. Nguyen
Keyword(s):  
Fully Depleted ◽  
Soi Technology
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