Realization of Logic Functions Using Switching Lattices Under a Delay Constraint

2020 ◽  
pp. 1-1
Author(s):  
Levent Aksoy ◽  
Nihat Akkan ◽  
Herman Sedef ◽  
Mustafa Altun
Keyword(s):  
Delay Constraint ◽  
Logic Functions

High-Density Memristor-CMOS Ternary Logic Family

2020 ◽  
Author(s):  
Xiaoyuan Wang ◽  
Pengfei Zhou ◽  
Jason Eshraghian ◽  
Chih-Yang Lin ◽  
Herbert Ho-Ching Iu ◽  
...  
Keyword(s):  
Indium Tin Oxide ◽  
Practical Implementation ◽  
Switching Speed ◽  
High Data ◽  
Fast Switching ◽  
Data Density ◽  
Order Of Magnitude ◽  
High Transconductance ◽  
Logic Functions ◽  
Magnitude Improvement

<div>This paper presents the first experimental demonstration</div><div>of a ternary memristor-CMOS logic family. We systematically</div><div>design, simulate and experimentally verify the primitive</div><div>logic functions: the ternary AND, OR and NOT gates. These are then used to build combinational ternary NAND, NOR, XOR and XNOR gates, as well as data handling ternary MAX and MIN gates. Our simulations are performed using a 50-nm process which are verified with in-house fabricated indium-tin-oxide memristors, optimized for fast switching, high transconductance, and low current leakage. We obtain close to an order of magnitude improvement in data density over conventional CMOS logic, and a reduction of switching speed by a factor of 13 over prior state-of-the-art ternary memristor results. We anticipate extensions of this work can realize practical implementation where high data density is of critical importance.</div>

Distributed Opportunistic Scheduling For Ad-Hoc Communications Under Delay Constraint

2010 ◽  
Author(s):  
Sheu-Sheu Tan ◽  
Dong Zheng ◽  
Junsham Zhang ◽  
James Zeidler
Keyword(s):  
Ad Hoc ◽  
Opportunistic Scheduling ◽  
Delay Constraint

scholarly journals Skyrmion Logic-In-Memory Architecture for Maximum/Minimum Search

Electronics ◽  
2021 ◽  
Vol 10 (2) ◽  
pp. 155
Author(s):  
Luca Gnoli ◽  
Fabrizio Riente ◽  
Marco Vacca ◽  
Massimo Ruo Roch ◽  
Mariagrazia Graziano
Keyword(s):  
High Efficiency ◽  
Digital Design ◽  
Control Logic ◽  
Minimum Number ◽  
Physical Simulations ◽  
Good Energy ◽  
Logic Functions ◽  
Time And Energy ◽  
Cmos Implementation ◽  
Maximum Minimum

In modern computing systems there is the need to utilize a large amount of data in maintaining high efficiency. Limited memory bandwidth, coupled with the performance gap between memory and logic, impacts heavily on algorithms performance, increasing the overall time and energy required for computation. A possible approach to overcome such limitations is Logic-In-Memory (LIM). In this paper, we propose a LIM architecture based on a non-volatile skyrmion-based recetrack memory. The architecture can be used as a memory or can perform advanced logic functions on the stored data, for example searching for the maximum/minimum number. The circuit has been designed and validated using physical simulations for the memory array together with digital design tools for the control logic. The results highlight the small area of the proposed architecture and its good energy efficiency compared with a reference CMOS implementation.

scholarly journals Training an asymmetric signal perceptron through reinforcement in an artificial chemistry

2014 ◽  
Vol 11 (93) ◽  
pp. 20131100 ◽  
Author(s):  
Peter Banda ◽  
Christof Teuscher ◽  
Darko Stefanovic
Keyword(s):  
State Of The Art ◽  
Chemical Species ◽  
Mass Action ◽  
Mass Action Kinetics ◽  
Dna Strand Displacement ◽  
Autonomous Adaptation ◽  
Biochemical Systems ◽  
Dna Strand ◽  
Logic Functions ◽  
Application Specific

State-of-the-art biochemical systems for medical applications and chemical computing are application-specific and cannot be reprogrammed or trained once fabricated. The implementation of adaptive biochemical systems that would offer flexibility through programmability and autonomous adaptation faces major challenges because of the large number of required chemical species as well as the timing-sensitive feedback loops required for learning. In this paper, we begin addressing these challenges with a novel chemical perceptron that can solve all 14 linearly separable logic functions. The system performs asymmetric chemical arithmetic, learns through reinforcement and supports both Michaelis–Menten as well as mass-action kinetics. To enable cascading of the chemical perceptrons, we introduce thresholds that amplify the outputs. The simplicity of our model makes an actual wet implementation, in particular by DNA-strand displacement, possible.

A Shared Path Protection Mechanism Based on Delay Constraint in the Optical Network

2013 ◽  
Vol 427-429 ◽  
pp. 2237-2244
Author(s):  
Jie Li ◽  
Xing Wei Wang ◽  
Min Huang
Keyword(s):  
Real Time ◽  
Optical Network ◽  
Propagation Delay ◽  
Wavelength Assignment ◽  
Delay Constraint ◽  
Protection Mechanism ◽  
Path Protection ◽  
Important Concern ◽  
Efficient Protection ◽  
Shared Path Protection

Survivability is an important concern in the optical network. In order to offer an effective and efficient protection mechanism that meeting both delay constraint and availability guarantees for real-time services in the optical network, a shared path protection mechanism based on delay constraint is proposed in this paper. Thinking of the processing delay and the propagation delay as main factors which have great effect on the delay of real-time services, the mechanism designs the routing and wavelength assignment schemes for the working path and the protection path. Simulation results show that the proposed mechanism is both feasible and effective.

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