On representation of k-valued logic functions by a sum of products of subfunctions

2007 ◽  
Vol 17 (3) ◽  
Author(s):  
V. I. Panteleev ◽  
N. A. Peryazev
Keyword(s):  
Sum Of Products ◽  
Logic Functions

scholarly journals Design and Construction of 3 x 3 Bits Programmable Logic Array (PLA) Circuit

2020 ◽  
pp. 179-183
Author(s):  
Sanda Win ◽  
San San Htwe ◽  
Sandar Win ◽  
Myint Myint Swe
Keyword(s):  
Logic Circuits ◽  
Programmable Logic ◽  
Canonical Forms ◽  
Logic Device ◽  
Programmable Logic Array ◽  
Sum Of Products ◽  
Combinational Logic Circuits ◽  
Input Variables ◽  
Logic Functions ◽  
Logic Array

A programmable logic array (PLA) is a kind of programmable logic device used to implement combinational logic circuits. The PLA has a set of programmable AND gate planes, which link to a set of programmable OR gate planes, which can then be conditionally complemented to produce an output. It has 2N AND gate s for N input variables and for M outputs from PLA, there should be M OR gates, each with programmable inputs from all of the AND gates. This layout allows for many logic functions to be synthesized in the sum of products canonical forms. The Programmable Logic Array (PLA) has a programmable AND array followed by a programmable OR array. Programmable Logic Array (PLA) circuit is built by using AND gates and OR gates. The 3x 4 bits data can be stored in this circuit. The large storage data bits of PLA circuit store by a using large AND-OR array with lots of inputs and product terms, and programmable connections. Programmable Logic Array circuit functions as ROM circuit.

scholarly journals An extended Green-Sasao hierarchy of canonical ternary Galois forms and Universal Logic Modules

2017 ◽  
Vol 30 (1) ◽  
pp. 49-66
Author(s):  
Anas Al-Rabadi
Keyword(s):  
Logic Synthesis ◽  
Galois Field ◽  
Input Output ◽  
Universal Logic ◽  
Binary Case ◽  
Sum Of Products ◽  
Logic Modules ◽  
The Many ◽  
Logic Functions ◽  
Spectral Transforms

A new extended Green-Sasao hierarchy of families and forms with a new sub-family for many-valued Reed-Muller logic is introduced. Recently, two families of binary canonical Reed-Muller forms, called Inclusive Forms (IFs) and Generalized Inclusive Forms (GIFs) have been proposed, where the second family was the first to include all minimum Exclusive Sum-Of-Products (ESOPs). In this paper, we propose, analogously to the binary case, two general families of canonical ternary Reed-Muller forms, called Ternary Inclusive Forms (TIFs) and their generalization of Ternary Generalized Inclusive Forms (TGIFs), where the second family includes minimum Galois Field Sum-Of-Products (GFSOPs) over ternary Galois field GF(3). One of the basic motivations in this work is the application of these TIFs and TGIFs to find the minimum GFSOP for many-valued input-output functions within logic synthesis, where a GFSOP minimizer based on IF polarity can be used to minimize the many-valued GFSOP expression for any given function. The realization of the presented S/D trees using Universal Logic Modules (ULMs) is also introduced, whereULMs are complete systems that can implement all possible logic functions utilizing the corresponding S/D expansions of many-valued Shannon and Davio spectral transforms.

High-Density Memristor-CMOS Ternary Logic Family

2020 ◽  
Author(s):  
Xiaoyuan Wang ◽  
Pengfei Zhou ◽  
Jason Eshraghian ◽  
Chih-Yang Lin ◽  
Herbert Ho-Ching Iu ◽  
...  
Keyword(s):  
Indium Tin Oxide ◽  
Practical Implementation ◽  
Switching Speed ◽  
High Data ◽  
Fast Switching ◽  
Data Density ◽  
Order Of Magnitude ◽  
High Transconductance ◽  
Logic Functions ◽  
Magnitude Improvement

<div>This paper presents the first experimental demonstration</div><div>of a ternary memristor-CMOS logic family. We systematically</div><div>design, simulate and experimentally verify the primitive</div><div>logic functions: the ternary AND, OR and NOT gates. These are then used to build combinational ternary NAND, NOR, XOR and XNOR gates, as well as data handling ternary MAX and MIN gates. Our simulations are performed using a 50-nm process which are verified with in-house fabricated indium-tin-oxide memristors, optimized for fast switching, high transconductance, and low current leakage. We obtain close to an order of magnitude improvement in data density over conventional CMOS logic, and a reduction of switching speed by a factor of 13 over prior state-of-the-art ternary memristor results. We anticipate extensions of this work can realize practical implementation where high data density is of critical importance.</div>

scholarly journals On the Ternary Exponential Diophantine Equation Equating a Perfect Power and Sum of Products of Consecutive Integers

Mathematics ◽  
2021 ◽  
Vol 9 (15) ◽  
pp. 1813
Author(s):  
S. Subburam ◽  
Lewis Nkenyereye ◽  
N. Anbazhagan ◽  
S. Amutha ◽  
M. Kameswari ◽  
...  
Keyword(s):  
Positive Integer ◽  
Diophantine Equation ◽  
Upper Bound ◽  
Exponential Diophantine Equation ◽  
Research Article ◽  
All Solutions ◽  
Sum Of Products ◽  
Consecutive Integers ◽  
Sums Of Products ◽  
Positive Integers

Consider the Diophantine equation yn=x+x(x+1)+⋯+x(x+1)⋯(x+k), where x, y, n, and k are integers. In 2016, a research article, entitled – ’power values of sums of products of consecutive integers’, primarily proved the inequality n= 19,736 to obtain all solutions (x,y,n) of the equation for the fixed positive integers k≤10. In this paper, we improve the bound as n≤ 10,000 for the same case k≤10, and for any fixed general positive integer k, we give an upper bound depending only on k for n.

scholarly journals Skyrmion Logic-In-Memory Architecture for Maximum/Minimum Search

Electronics ◽  
2021 ◽  
Vol 10 (2) ◽  
pp. 155
Author(s):  
Luca Gnoli ◽  
Fabrizio Riente ◽  
Marco Vacca ◽  
Massimo Ruo Roch ◽  
Mariagrazia Graziano
Keyword(s):  
High Efficiency ◽  
Digital Design ◽  
Control Logic ◽  
Minimum Number ◽  
Physical Simulations ◽  
Good Energy ◽  
Logic Functions ◽  
Time And Energy ◽  
Cmos Implementation ◽  
Maximum Minimum

In modern computing systems there is the need to utilize a large amount of data in maintaining high efficiency. Limited memory bandwidth, coupled with the performance gap between memory and logic, impacts heavily on algorithms performance, increasing the overall time and energy required for computation. A possible approach to overcome such limitations is Logic-In-Memory (LIM). In this paper, we propose a LIM architecture based on a non-volatile skyrmion-based recetrack memory. The architecture can be used as a memory or can perform advanced logic functions on the stored data, for example searching for the maximum/minimum number. The circuit has been designed and validated using physical simulations for the memory array together with digital design tools for the control logic. The results highlight the small area of the proposed architecture and its good energy efficiency compared with a reference CMOS implementation.

Lower bounds for Sum and Sum of Products of Read-once Formulas

2019 ◽  
Vol 11 (2) ◽  
pp. 1-27 ◽  
Author(s):  
C. Ramya ◽  
B. V. Raghavendra Rao
Keyword(s):  
Lower Bounds ◽  
Sum Of Products

scholarly journals Training an asymmetric signal perceptron through reinforcement in an artificial chemistry

2014 ◽  
Vol 11 (93) ◽  
pp. 20131100 ◽  
Author(s):  
Peter Banda ◽  
Christof Teuscher ◽  
Darko Stefanovic
Keyword(s):  
State Of The Art ◽  
Chemical Species ◽  
Mass Action ◽  
Mass Action Kinetics ◽  
Dna Strand Displacement ◽  
Autonomous Adaptation ◽  
Biochemical Systems ◽  
Dna Strand ◽  
Logic Functions ◽  
Application Specific

State-of-the-art biochemical systems for medical applications and chemical computing are application-specific and cannot be reprogrammed or trained once fabricated. The implementation of adaptive biochemical systems that would offer flexibility through programmability and autonomous adaptation faces major challenges because of the large number of required chemical species as well as the timing-sensitive feedback loops required for learning. In this paper, we begin addressing these challenges with a novel chemical perceptron that can solve all 14 linearly separable logic functions. The system performs asymmetric chemical arithmetic, learns through reinforcement and supports both Michaelis–Menten as well as mass-action kinetics. To enable cascading of the chemical perceptrons, we introduce thresholds that amplify the outputs. The simplicity of our model makes an actual wet implementation, in particular by DNA-strand displacement, possible.

Programming Cell Adhesion for On-Chip Sequential Boolean Logic Functions

2017 ◽  
Vol 139 (30) ◽  
pp. 10176-10179 ◽  
Author(s):  
Xiangmeng Qu ◽  
Shaopeng Wang ◽  
Zhilei Ge ◽  
Jianbang Wang ◽  
Guangbao Yao ◽  
...  
Keyword(s):  
Cell Adhesion ◽  
Boolean Logic ◽  
On Chip ◽  
Logic Functions
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