Robust Ultra-Low Power Non-Volatile Logic-in-Memory Circuits in FD-SOI Technology

IEEE Transactions on Circuits and Systems I Regular Papers ◽

10.1109/tcsi.2016.2621344 ◽

2017 ◽

Vol 64 (4) ◽

pp. 847-857 ◽

Author(s):

Hao Cai ◽

You Wang ◽

Lirida Alves De Barros Naviner ◽

Weisheng Zhao

Keyword(s):

Low Power ◽

Ultra Low Power ◽

Memory Circuits ◽

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An ultra low power consumption millimeter-wave voltage controlled oscillator in a 65 nm CMOS-SOI technology

Analog Integrated Circuits and Signal Processing ◽

10.1007/s10470-013-0040-z ◽

2013 ◽

Vol 76 (3) ◽

pp. 277-286 ◽

Author(s):

A. Mariano ◽

O. Mazouffre ◽

B. Leite ◽

Y. Deval ◽

J. B. Begueret ◽

...

Keyword(s):

Power Consumption ◽

Low Power ◽

Millimeter Wave ◽

Low Power Consumption ◽

Voltage Controlled Oscillator ◽

Ultra Low Power ◽

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Ultra low-power CMOS IC using partially-depleted SOI technology

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) ◽

10.1109/cicc.2000.852617 ◽

2002 ◽

Author(s):

A. Ebina ◽

T. Kadowaki ◽

Y. Sato ◽

M. Yamaguchi

Keyword(s):

Low Power ◽

Ultra Low Power ◽

Low Power Cmos ◽

Cmos Ic ◽

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22nm FD-SOI Technology with Back-biasing Capability Offers Excellent Performance for Enabling Efficient, Ultra-low Power Analog and RF/Millimeter-Wave Designs

2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) ◽

10.1109/rfic.2019.8701768 ◽

2019 ◽

Author(s):

S.N. Ong ◽

L.H.K. Chan ◽

K.W.J. Chew ◽

C.K. Lim ◽

W. L. Oo ◽

...

Keyword(s):

Low Power ◽

Millimeter Wave ◽

Excellent Performance ◽

Ultra Low Power ◽

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An ultra-low power Dual-Ring factorial Delay Locked Loop in 28nm FD-SOI technology

2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) ◽

10.1109/icsict.2016.7998978 ◽

2016 ◽

Author(s):

Khoa Hoang ◽

Yann Deval ◽

Francois Rivet

Keyword(s):

Low Power ◽

Ultra Low Power ◽

Delay Locked Loop ◽

Soi Technology ◽

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Fully Depleted SOI Technology for Ultra Low Power Application

10.7567/ssdm.2004.c-5-2 ◽

2004 ◽

Author(s):

Fumio Ichikawa ◽

Shunsuke Baba

Keyword(s):

Low Power ◽

Ultra Low Power ◽

Fully Depleted ◽

Power Application ◽

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Ultra-Low Power Radiation Hardened by Design Memory Circuits

IEEE Transactions on Nuclear Science ◽

10.1109/tns.2007.909909 ◽

2007 ◽

Vol 54 (6) ◽

pp. 2004-2011 ◽

Author(s):

Tai-Hua Chen ◽

Jinhui Chen ◽

Lawrence T. Clark ◽

Jonathan E. Knudsen ◽

Giby Samson

Keyword(s):

Low Power ◽

Ultra Low Power ◽

Memory Circuits ◽

Radiation Hardened ◽

Radiation Hardened By Design ◽

Power Radiation

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Ultra Low Power 3-D Flow Meter in Monolithic SOI Technology

ECS Transactions ◽

10.1149/1.3570812 ◽

2019 ◽

Vol 35 (5) ◽

pp. 319-324 ◽

Author(s):

Nicolas Andre ◽

Bertrand Rue ◽

Gilles Scheen ◽

Laurent A. Francis ◽

Denis Flandre ◽

...

Keyword(s):

Low Power ◽

Ultra Low Power ◽

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Ultra Low Power 3-D Flow Meter in Monolithic SOI Technology

ECS Meeting Abstracts ◽

10.1149/ma2011-01/23/1459 ◽

2011 ◽

Keyword(s):

Low Power ◽

Ultra Low Power ◽

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Building ultra-low-power high-temperature digital circuits in standard high-performance SOI technology

Solid-State Electronics ◽

10.1016/j.sse.2008.06.045 ◽

2008 ◽

Vol 52 (12) ◽

pp. 1939-1945 ◽

Author(s):

David Bol ◽

Julien De Vos ◽

Renaud Ambroise ◽

Denis Flandre ◽

Jean-Didier Legat

Keyword(s):

High Temperature ◽

Low Power ◽

High Performance ◽

Digital Circuits ◽

Ultra Low Power ◽

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Design-space exploration of ultra-low power CMOS logic gates in a 28 nm FD-SOI technology

2017 European Conference on Circuit Theory and Design (ECCTD) ◽

10.1109/ecctd.2017.8093232 ◽

2017 ◽

Author(s):

Marten Vohrmann ◽

Philippe Geisler ◽

Thorsten Jungeblut ◽

Ulrich Ruckert

Keyword(s):

Low Power ◽

Design Space Exploration ◽

Design Space ◽

Space Exploration ◽

Logic Gates ◽

Ultra Low Power ◽

Low Power Cmos ◽

Soi Technology ◽

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