A Low-Power 8-GS/s Comparator for High-Speed Analog-to-Digital Conversion in $0.13\mu$ m CMOS Technology

2019 ◽  
Vol 66 (4) ◽  
pp. 557-561
Author(s):  
Darya Mohtashemi ◽  
Michael M. Green
2007 ◽  
Vol 16 (01) ◽  
pp. 1-14
Author(s):  
TASKIN KOCAK ◽  
GEORGE R. HARRIS ◽  
RONALD F. DEMARA

In this paper, a novel architecture for self-timed analog-to-digital conversion is presented and designed using the NULL Convention Logic (NCL) paradigm. This analog-to-digital converter (ADC) employs successive approximation and a one-hot encoded masking technique to digitize analog signals. The architecture scales readily to any given resolution by utilizing the one-hot encoded scheme to permit identical logical components for each bit of resolution. The four-bit configuration of the proposed design has been implemented and assessed via simulation in 0.18-μm CMOS technology. Furthermore, the ADC may be interfaced with either synchronous or four-phase asynchronous digital systems.


2009 ◽  
Author(s):  
C. W. Holzwarth ◽  
R. Amatya ◽  
M. Araghchini ◽  
J. Birge ◽  
H. Byun ◽  
...  

2005 ◽  
Author(s):  
Henry Zmuda ◽  
Shane Hanna ◽  
R. J. Bussjager ◽  
M. L. Fanto ◽  
M. J. Hayduk ◽  
...  

2011 ◽  
Vol 38 (1) ◽  
pp. 0105006
Author(s):  
窦玉杰 Dou Yujie ◽  
张洪明 Zhang Hongming ◽  
傅鑫 Fu Xin ◽  
姚敏玉 Yao Minyu

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