Performance Limitation Analysis of Highly-Digital Time-Based Closed-Loop Sensor-to-Digital Converter Architectures

IEEE Transactions on Circuits & Systems II Express Briefs ◽

10.1109/tcsii.2018.2880258 ◽

2019 ◽

Vol 66 (7) ◽

pp. 1114-1118 ◽

Author(s):

Elisa Sacco ◽

Jorge Marin ◽

Johan Vergauwen ◽

Georges Gielen

Keyword(s):

Closed Loop ◽

Digital Converter ◽

Performance Limitation ◽

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Architectural Analysis of a Novel Closed-Loop VCO-Based 1–1 Sturdy MASH Sensor-to-Digital Converter

2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) ◽

10.1109/smacd.2019.8795290 ◽

2019 ◽

Author(s):

Elisa Sacco ◽

Johan Vergauwen ◽

Georges Gielen

Keyword(s):

Closed Loop ◽

Digital Converter ◽

Architectural Analysis

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From Open-Loop to Closed-Loop Single-VCO-Based Sensor-to-Digital Converter Architectures: theoretical analysis and comparison

2019 IEEE 8th International Workshop on Advances in Sensors and Interfaces (IWASI) ◽

10.1109/iwasi.2019.8791296 ◽

2019 ◽

Author(s):

Elisa Sacco ◽

Johan Vergauwen ◽

Georges Gielen

Keyword(s):

Theoretical Analysis ◽

Closed Loop ◽

Open Loop ◽

Digital Converter

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A 6-bit 100-MS/s Fully-Digital Time-Based Analog-to-Digital Converter

2019 27th Iranian Conference on Electrical Engineering (ICEE) ◽

10.1109/iraniancee.2019.8786439 ◽

2019 ◽

Author(s):

Hassan Rivandi ◽

Fatemeh Shakibaee ◽

Mehdi Saberi

Keyword(s):

Analog To Digital Converter ◽

Digital Converter ◽

Analog To Digital ◽

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A standard cell based all-digital Time-to-Digital Converter with reconfigurable resolution and on-line background calibration

2011 Proceedings of the ESSCIRC (ESSCIRC) ◽

10.1109/esscirc.2011.6044960 ◽

2011 ◽

Author(s):

Kameswaran Vengattaramane ◽

Jonathan Borremans ◽

Michiel Steyaert ◽

Jan Craninckx

Keyword(s):

Standard Cell ◽

Background Calibration ◽

Digital Converter ◽

Time To Digital Converter ◽

On Line ◽

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Time‐based all‐digital time‐to‐digital converter with pre‐skewed bi‐directional gated delay line time integrator

IET Circuits Devices & Systems ◽

10.1049/iet-cds.2019.0108 ◽

2019 ◽

Vol 14 (1) ◽

pp. 25-34 ◽

Author(s):

Fei Yuan ◽

Parth Parekh

Keyword(s):

Digital Converter ◽

Time To Digital Converter ◽

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An FPGA-based Closed-loop Approach of Angular Displacement for a Resolver-to-Digital-Converter

2018 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas.2018.8351325 ◽

2018 ◽

Author(s):

Juan Yepez ◽

Xiaofeng Shi ◽

Seok-Bum Ko

Keyword(s):

Closed Loop ◽

Angular Displacement ◽

Digital Converter

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A Second-Order $\Delta\Sigma$ Time-to-Digital Converter Using Highly Digital Time-Domain Arithmetic Circuits

IEEE Transactions on Circuits & Systems II Express Briefs ◽

10.1109/tcsii.2019.2925860 ◽

2019 ◽

Vol 66 (10) ◽

pp. 1643-1647

Author(s):

Dongin Kim ◽

Kwangseok Kim ◽

Wonsik Yu ◽

Seonghwan Cho

Keyword(s):

Time Domain ◽

Second Order ◽

Arithmetic Circuits ◽

Digital Converter ◽

Time To Digital Converter ◽

Delta Sigma ◽

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Fully-Digital Time-To-Digital Converter for ATE with Autonomous Calibration

2006 IEEE International Test Conference ◽

10.1109/test.2006.297713 ◽

2006 ◽

Author(s):

Jochen Rivoir

Keyword(s):

Digital Converter ◽

Time To Digital Converter ◽

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All digital time-to-digital converter using single delay-locked loop

2008 IEEE International SOC Conference ◽

10.1109/socc.2008.4641541 ◽

2008 ◽

Author(s):

Hong-Yi Huang ◽

Yi-Jui Tsai ◽

Kung-Liang Ho ◽

Chan-Yu Lin

Keyword(s):

Digital Converter ◽

Time To Digital Converter ◽

Delay Locked Loop ◽

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Performance limitation of closed-loop transmit antenna diversity over fast Rayleigh fading channels

IEEE Transactions on Vehicular Technology ◽

10.1109/tvt.2002.1015356 ◽

2002 ◽

Vol 51 (4) ◽

pp. 771-775 ◽

Author(s):

Jinho Choi

Keyword(s):

Fading Channels ◽

Rayleigh Fading ◽

Closed Loop ◽

Rayleigh Fading Channels ◽

Antenna Diversity ◽

Performance Limitation

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