A 0.03- to 3.6-GHz Frequency Synthesizer With Self-Biased VCO and Quadrature-Input Quadrature-Output Frequency Divider

2019 ◽  
Vol 66 (12) ◽  
pp. 1997-2001 ◽  
Author(s):  
Ang Hu ◽  
Dongsheng Liu ◽  
Kefeng Zhang
Keyword(s):  
Frequency Synthesizer ◽  
Frequency Divider ◽  
Output Frequency

scholarly journals An Interpolated Flying-Adder-Based Frequency Synthesizer

2011 ◽  
Vol 2011 ◽  
pp. 1-11 ◽  
Author(s):  
Pao-Lung Chen ◽  
Chun-Chien Tsai
Keyword(s):  
Root Mean Square ◽  
Frequency Synthesizer ◽  
Phase Locked Loop ◽  
Cmos Technology ◽  
Core Area ◽  
Mean Square ◽  
Output Frequency ◽  
Test Chip ◽  
The Core ◽  
Reference Signals

This work presents an interpolated flying-adder- (FA-) based frequency synthesizer. The architecture of an interpolated FA, which uses an interpolated multiplexer (MUX) to replace the multiplexer in conventional flying adder, improves the cycle-to-cycle jitter and root-mean-square (RMS) jitter performance. A multiphase all-digital phase-locked loop (ADPLL) provides steady reference signals for the interpolated flying adder. This paper reveals implementation skills of a multiphase ADPLL, as well as an interpolated flying adder. In addition, analytical details of the jitter performance are derived. A test chip for the proposed interpolated FA-based frequency synthesizer was fabricated in a standard 0.18 μm CMOS technology, and the core area was 0.143 mm2. The output frequency had a range of 33 MHz ~ 286 MHz at 1.8 V with peak-to-peak (Pk-Pk) jitter 215.2 ps at 286 MHz/1.8 V.

A 21.68 GHz low-power frequency synthesizer chip design with an injection-locked frequency divider

2012 ◽  
Vol 55 (1) ◽  
pp. 200-205 ◽  
Author(s):  
Jhin-Fang Huang ◽  
Chien-Ming Hsu ◽  
Kuo-Lung Chen ◽  
Ron-Yi Liu
Keyword(s):  
Low Power ◽  
Frequency Synthesizer ◽  
Frequency Divider ◽  
Chip Design ◽  
Power Frequency
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