Fault Injection in Modern Microprocessors Using On-Chip Debugging Infrastructures

Increased access to space has led to an increase in the usage of commodity processors in radiation environments. These processors are vulnerable to transient faults such as single event upsets that may cause bit-flips in processor components. Caches in particular are vulnerable due to their relatively large area, yet are often omitted from fault injection testing because many processors do not provide direct access to cache contents and they are often not fully modeled by simulators. The performance benefits of caches make disabling them undesirable, and the presence of error correcting codes is insufficient to correct for increasingly common multiple bit upsets. This work explores building a program’s cache profile by collecting cache usage information at an instruction granularity via commonly available on-chip debugging interfaces. The profile provides a tighter bound than cache utilization for cache vulnerability estimates (50% for several benchmarks). This can be applied to reduce the number of fault injections required to characterize behavior by at least two-thirds for the benchmarks we examine. The profile enables future work in hardware fault injection for caches that avoids the biases of existing techniques.

Download Full-text

Test mode method and strategy for RF-based fault injection analysis for on-chip relaxation oscillators under EMC standard tests or RFI susceptibility characterization

2010 11th Latin American Test Workshop ◽

10.1109/latw.2010.5550382 ◽

2010 ◽

Cited By ~ 1

Author(s):

A. Olmos ◽

A. Vilas Boas ◽

E. R. da Silva ◽

J. C. Silva ◽

R. Maltione

Keyword(s):

Fault Injection ◽

Test Mode ◽

Relaxation Oscillators ◽

Mode Method ◽

On Chip ◽

Standard Tests

Download Full-text

An on-chip glitchy-clock generator for testing fault injection attacks

Journal of Cryptographic Engineering ◽

10.1007/s13389-011-0022-y ◽

2011 ◽

Vol 1 (4) ◽

pp. 265-270 ◽

Cited By ~ 35

Author(s):

Sho Endo ◽

Takeshi Sugawara ◽

Naofumi Homma ◽

Takafumi Aoki ◽

Akashi Satoh

Keyword(s):

Fault Injection ◽

Clock Generator ◽

Injection Attacks ◽

On Chip ◽

Fault Injection Attacks

Download Full-text

Fault injection via on-chip debugging in the internal memory of systems-on-chip processor

IOP Conference Series Materials Science and Engineering ◽

10.1088/1757-899x/94/1/012020 ◽

2015 ◽

Vol 94 ◽

pp. 012020 ◽

Cited By ~ 3

Author(s):

S A Chekmarev ◽

V Kh Khanov

Keyword(s):

Fault Injection ◽

Internal Memory ◽

Systems On Chip ◽

On Chip

Download Full-text

Modification of fault injection method via on-chip debugging for processor cores of systems-on-chip

2015 International Siberian Conference on Control and Communications (SIBCON) ◽

10.1109/sibcon.2015.7147267 ◽

2015 ◽

Cited By ~ 4

Author(s):

S.A. Chekmarev ◽

V.Kh. Khanov ◽

O.A. Antamoshkin

Keyword(s):

Fault Injection ◽

Injection Method ◽

Systems On Chip ◽

On Chip ◽

Processor Cores

Download Full-text

Countermeasures against physical security attacks on ICs utilizing on-chip wideband ADCs

Japanese Journal of Applied Physics ◽

10.35848/1347-4065/ac4823 ◽

2022 ◽

Author(s):

Takuji Miki ◽

Makoto Nagata

Keyword(s):

Active Fault ◽

Fault Injection ◽

Side Channel ◽

Security Attacks ◽

Input Buffer ◽

Analog To Digital ◽

Side Channel Analysis ◽

Measurement Results ◽

Channel Analysis ◽

On Chip

Abstract Cryptographic ICs on edge devices for internet-of-things (IoT) applications are exposed to an adversary and threatened by malicious side channel analysis. On-chip analog monitoring by sensor circuits embedded inside the chips is one of the possible countermeasures against such attacks. An on-chip monitor circuit consisting of a successive approximation register (SAR) analog-to-digital converter (ADC) and an input buffer acquires a wideband signal, which enables to detects an irregular noise due to an active fault injection and a passive side channel leakage analysis. In this paper, several countermeasures against security attacks utilizing wideband on-chip monitors are reviewed. Each technique is implemented on a prototype chip, and the measurement results prove they can effectively detect and diagnose the security attacks.

Download Full-text

NoCFI: A Hybrid Fault Injection Method for Networks-On-Chip

2019 IEEE Latin American Test Symposium (LATS) ◽

10.1109/latw.2019.8704559 ◽

2019 ◽

Author(s):

Alexandre Coelho ◽

Nacer-Eddine Zergainoh ◽

Raoul Velazco

Keyword(s):

Fault Injection ◽

Networks On Chip ◽

Injection Method ◽

On Chip

Download Full-text

Virtual Verification and Validation of Automotive System

Journal of Circuits System and Computers ◽

10.1142/s0218126619500713 ◽

2019 ◽

Vol 28 (04) ◽

pp. 1950071

Author(s):

Mona Safar ◽

Magdy A. El-Moursy ◽

Mohamed Abdelsalam ◽

Ayman Bakr ◽

Keroles Khalil ◽

...

Keyword(s):

Fault Injection ◽

Electronic Control Unit ◽

Control Unit ◽

Verification And Validation ◽

System Level ◽

Development Cycle ◽

Virtual Platform ◽

On Chip ◽

Automotive System

An integrated framework for Virtual Verification and Validation (VVV) for a complete automotive system is proposed. The framework can simulate/emulate the system on three levels: System on Chip (SoC), Electronic control unit (ECU) and system level. The framework emulates the real system including hardware (HW) and software (SW). It enhances the automotive V-cycle and allows co-development of the automotive system SW and HW. The procedure for debugging AUTOSAR application on the virtual platform (VP) is shown. SW and HW profiling is feasible with the presented methodology. Verification and validation of automotive embedded SW is also presented. The proposed methodology is efficient as the system complexity increases which shortens the development cycle of automotive system. It also provides fault injection capability. With HW emulation, co-debugging mechanism is demonstrated. A case study covering the framework capability is presented. The case study demonstrates the proposed framework and methodology to design, simulate, trace, profile and debug AUTOSAR SW using VPs.

Download Full-text