Al/SiC Carriers for Microwave Integrated Circuits by a New Technique of Pressureless Infiltration

2006 ◽  
Vol 29 (1) ◽  
pp. 58-63 ◽  
Author(s):  
B.S. Rao ◽  
C. Hemambar ◽  
A.V. Pathak ◽  
K.J. Patel ◽  
J. Rodel ◽  
...  
Author(s):  
G. LAKSHMI PRANEETHA ◽  
P. HAREESH

In this paper a new technique is proposed based on the comparison between Conventional Transistorized Flip-flop and Data transition Look ahead D flip flop here we are checking the working of DLDFF and the conventional D Flip-flop after that we are analyzing the characteristic comparison using power & area constraints after that we are proposing a Negative Edge triggered flip-flop named as Switching Transistor based D Flip-Flop(STDFF) with reduced number of transistors which will reduce the overall power area as well as delay. The simulations are done using Microwind & DSCH analysis software tools and the result between all those types are listed below. Our proposed system simulations are done under 50nm technology and the results are tabulated below. In that our proposed system is showing better output than the other flip-flops compared here.


Author(s):  
Richard G. Sartore

In the evaluation of GaAs devices from the MMIC (Monolithic Microwave Integrated Circuits) program for Army applications, there was a requirement to obtain accurate linewidth measurements on the nominal 0.5 micrometer gate lengths used to fabricate these devices. Preliminary measurements indicated a significant variation (typically 10 % to 30% but could be more) in the critical dimensional measurements of the gate length, gate to source distance and gate to drain distance. Passivation introduced a margin of error, which was removed by plasma etching. Additionally, the high aspect ratio (4-5) of the thick gold (Au) conductors also introduced measurement difficulties. The final measurements were performed after the thick gold conductor was removed and only the barrier metal remained, which was approximately 250 nanometer thick platinum on GaAs substrate. The thickness was measured using the penetration voltage method. Linescan of the secondary electron signal as it scans across the gate is shown in Figure 1.


2005 ◽  
Vol 25 (1_suppl) ◽  
pp. S543-S543
Author(s):  
Satoshi Kimura ◽  
Keigo Matsumoto ◽  
Yoshio Imahori ◽  
Katsuyoshi Mineura ◽  
Toshiyuki Itoh

2009 ◽  
Vol 56 (S 01) ◽  
Author(s):  
J Bickenbach ◽  
R Rossaint ◽  
R Autschbach ◽  
R Dembinski

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